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@@ -49,6 +49,7 @@ struct socfpga_dwmac {
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u32 reg_shift;
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struct device *dev;
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struct regmap *sys_mgr_base_addr;
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+ struct reset_control *stmmac_rst;
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void __iomem *splitter_base;
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bool f2h_ptp_ref_clk;
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};
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@@ -135,7 +136,7 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *
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return 0;
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}
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-static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
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+static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
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{
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struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
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int phymode = dwmac->interface;
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@@ -164,6 +165,10 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
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if (dwmac->splitter_base)
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val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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+ /* Assert reset to the enet controller before changing the phy mode */
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+ if (dwmac->stmmac_rst)
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+ reset_control_assert(dwmac->stmmac_rst);
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+
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regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
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ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
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ctrl |= val << reg_shift;
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@@ -181,57 +186,13 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
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regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
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- return 0;
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-}
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-
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-static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
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-{
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- struct socfpga_dwmac *dwmac = priv;
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- struct net_device *ndev = platform_get_drvdata(pdev);
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- struct stmmac_priv *stpriv = NULL;
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- int ret = 0;
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-
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- if (!ndev)
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- return -EINVAL;
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-
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- stpriv = netdev_priv(ndev);
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- if (!stpriv)
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- return -EINVAL;
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-
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- /* Assert reset to the enet controller before changing the phy mode */
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- if (stpriv->stmmac_rst)
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- reset_control_assert(stpriv->stmmac_rst);
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-
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- /* Setup the phy mode in the system manager registers according to
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- * devicetree configuration
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- */
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- ret = socfpga_dwmac_setup(dwmac);
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-
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/* Deassert reset for the phy configuration to be sampled by
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* the enet controller, and operation to start in requested mode
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*/
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- if (stpriv->stmmac_rst)
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- reset_control_deassert(stpriv->stmmac_rst);
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-
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- /* Before the enet controller is suspended, the phy is suspended.
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- * This causes the phy clock to be gated. The enet controller is
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- * resumed before the phy, so the clock is still gated "off" when
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- * the enet controller is resumed. This code makes sure the phy
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- * is "resumed" before reinitializing the enet controller since
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- * the enet controller depends on an active phy clock to complete
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- * a DMA reset. A DMA reset will "time out" if executed
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- * with no phy clock input on the Synopsys enet controller.
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- * Verified through Synopsys Case #8000711656.
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- *
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- * Note that the phy clock is also gated when the phy is isolated.
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- * Phy "suspend" and "isolate" controls are located in phy basic
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- * control register 0, and can be modified by the phy driver
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- * framework.
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- */
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- if (stpriv->phydev)
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- phy_resume(stpriv->phydev);
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+ if (dwmac->stmmac_rst)
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+ reset_control_deassert(dwmac->stmmac_rst);
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- return ret;
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+ return 0;
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}
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static int socfpga_dwmac_probe(struct platform_device *pdev)
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@@ -261,16 +222,57 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
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}
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plat_dat->bsp_priv = dwmac;
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- plat_dat->init = socfpga_dwmac_init;
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plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
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ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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- if (!ret)
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- ret = socfpga_dwmac_init(pdev, dwmac);
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+ if (!ret) {
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+ struct net_device *ndev = platform_get_drvdata(pdev);
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+ struct stmmac_priv *stpriv = netdev_priv(ndev);
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+
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+ /* The socfpga driver needs to control the stmmac reset to
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+ * set the phy mode. Create a copy of the core reset handel
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+ * so it can be used by the driver later.
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+ */
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+ dwmac->stmmac_rst = stpriv->stmmac_rst;
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+
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+ ret = socfpga_dwmac_set_phy_mode(dwmac);
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+ }
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return ret;
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}
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+#ifdef CONFIG_PM_SLEEP
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+static int socfpga_dwmac_resume(struct device *dev)
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+{
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+ struct net_device *ndev = dev_get_drvdata(dev);
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+ struct stmmac_priv *priv = netdev_priv(ndev);
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+
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+ socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);
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+
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+ /* Before the enet controller is suspended, the phy is suspended.
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+ * This causes the phy clock to be gated. The enet controller is
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+ * resumed before the phy, so the clock is still gated "off" when
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+ * the enet controller is resumed. This code makes sure the phy
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+ * is "resumed" before reinitializing the enet controller since
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+ * the enet controller depends on an active phy clock to complete
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+ * a DMA reset. A DMA reset will "time out" if executed
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+ * with no phy clock input on the Synopsys enet controller.
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+ * Verified through Synopsys Case #8000711656.
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+ *
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+ * Note that the phy clock is also gated when the phy is isolated.
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+ * Phy "suspend" and "isolate" controls are located in phy basic
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+ * control register 0, and can be modified by the phy driver
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+ * framework.
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+ */
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+ if (priv->phydev)
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+ phy_resume(priv->phydev);
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+
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+ return stmmac_resume(dev);
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+}
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+#endif /* CONFIG_PM_SLEEP */
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+
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+SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend, socfpga_dwmac_resume);
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+
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static const struct of_device_id socfpga_dwmac_match[] = {
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{ .compatible = "altr,socfpga-stmmac" },
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{ }
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@@ -282,7 +284,7 @@ static struct platform_driver socfpga_dwmac_driver = {
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.remove = stmmac_pltfr_remove,
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.driver = {
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.name = "socfpga-dwmac",
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- .pm = &stmmac_pltfr_pm_ops,
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+ .pm = &socfpga_dwmac_pm_ops,
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.of_match_table = socfpga_dwmac_match,
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},
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};
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