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@@ -72,7 +72,7 @@ static struct clk ** const uart_clks[] __initconst = {
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NULL
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};
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-int __init mx31_clocks_init(unsigned long fref)
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+static void __init _mx31_clocks_init(unsigned long fref)
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{
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void __iomem *base;
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struct device_node *np;
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@@ -142,6 +142,12 @@ int __init mx31_clocks_init(unsigned long fref)
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imx_check_clocks(clk, ARRAY_SIZE(clk));
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+ clk_set_parent(clk[csi], clk[upll]);
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+ clk_prepare_enable(clk[emi_gate]);
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+ clk_prepare_enable(clk[iim_gate]);
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+ mx31_revision();
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+ clk_disable_unprepare(clk[iim_gate]);
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+
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np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
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if (np) {
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@@ -149,6 +155,13 @@ int __init mx31_clocks_init(unsigned long fref)
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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+}
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+
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+int __init mx31_clocks_init(void)
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+{
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+ u32 fref = 26000000; /* default */
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+
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+ _mx31_clocks_init(fref);
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clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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@@ -204,14 +217,8 @@ int __init mx31_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
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clk_register_clkdev(clk[iim_gate], "iim", NULL);
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- clk_set_parent(clk[csi], clk[upll]);
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- clk_prepare_enable(clk[emi_gate]);
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- clk_prepare_enable(clk[iim_gate]);
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- mx31_revision();
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- clk_disable_unprepare(clk[iim_gate]);
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imx_register_uart_clocks(uart_clks);
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-
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mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
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return 0;
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@@ -230,5 +237,7 @@ int __init mx31_clocks_init_dt(void)
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break;
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}
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- return mx31_clocks_init(fref);
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+ _mx31_clocks_init(fref);
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+
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+ return 0;
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}
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