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@@ -1079,6 +1079,8 @@ force:
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/* update display watermarks based on new power state */
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/* update display watermarks based on new power state */
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radeon_bandwidth_update(rdev);
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radeon_bandwidth_update(rdev);
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+ /* update displays */
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+ radeon_dpm_display_configuration_changed(rdev);
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/* wait for the rings to drain */
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/* wait for the rings to drain */
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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@@ -1095,9 +1097,6 @@ force:
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radeon_dpm_post_set_power_state(rdev);
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radeon_dpm_post_set_power_state(rdev);
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- /* update displays */
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- radeon_dpm_display_configuration_changed(rdev);
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-
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.single_display = single_display;
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rdev->pm.dpm.single_display = single_display;
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