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@@ -452,50 +452,50 @@ enum dwc2_ep0_state {
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* default described above.
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*/
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struct dwc2_core_params {
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- int otg_cap;
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+ u8 otg_cap;
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#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
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#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
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#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
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- int dma_desc_enable;
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- int dma_desc_fs_enable;
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- int speed;
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+ bool dma_desc_enable;
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+ bool dma_desc_fs_enable;
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+ u8 speed;
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#define DWC2_SPEED_PARAM_HIGH 0
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#define DWC2_SPEED_PARAM_FULL 1
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#define DWC2_SPEED_PARAM_LOW 2
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- int enable_dynamic_fifo;
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- int en_multiple_tx_fifo;
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- int host_rx_fifo_size;
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- int host_nperio_tx_fifo_size;
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- int host_perio_tx_fifo_size;
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- int max_transfer_size;
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- int max_packet_count;
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- int host_channels;
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- int phy_type;
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+ bool enable_dynamic_fifo;
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+ bool en_multiple_tx_fifo;
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+ u16 host_rx_fifo_size;
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+ u16 host_nperio_tx_fifo_size;
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+ u16 host_perio_tx_fifo_size;
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+ u32 max_transfer_size;
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+ u16 max_packet_count;
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+ u8 host_channels;
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+ u8 phy_type;
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#define DWC2_PHY_TYPE_PARAM_FS 0
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#define DWC2_PHY_TYPE_PARAM_UTMI 1
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#define DWC2_PHY_TYPE_PARAM_ULPI 2
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- int phy_utmi_width;
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- int phy_ulpi_ddr;
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- int phy_ulpi_ext_vbus;
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+ u8 phy_utmi_width;
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+ bool phy_ulpi_ddr;
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+ bool phy_ulpi_ext_vbus;
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#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
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#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
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- int i2c_enable;
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- int ulpi_fs_ls;
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- int host_support_fs_ls_low_power;
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- int host_ls_low_power_phy_clk;
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+ bool i2c_enable;
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+ bool ulpi_fs_ls;
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+ bool host_support_fs_ls_low_power;
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+ bool host_ls_low_power_phy_clk;
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#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
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#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
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- int ts_dline;
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- int reload_ctl;
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- int ahbcfg;
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- int uframe_sched;
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- int external_id_pin_ctl;
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- int hibernation;
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+ bool ts_dline;
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+ bool reload_ctl;
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+ u32 ahbcfg;
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+ bool uframe_sched;
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+ bool external_id_pin_ctl;
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+ bool hibernation;
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/*
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* The following parameters are *only* set via device
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