dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO debounce

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Allow the DT node to specify the time (in ms) that we need
to wait before sampling the DIR line.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt

@@ -27,6 +27,11 @@ clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt
      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
      achieve the funtionality of an exernal type-C plug flip mux.
 
+ - typec-dir-debounce: Number of milliseconds to wait before sampling
+     typec-dir-gpio. If not specified, the GPIO will be sampled ASAP.
+     Type-C spec states minimum CC pin debounce of 100 ms and maximum
+     of 200 ms.
+
 Required subnodes:
  - Clock Subnode: WIZ node should have '3' subnodes for each of the clock
      selects it supports. The clock subnodes should have the following names