ARM: dts: am57xx-beagle-x15-revc: Fix ddr pinmux names for mmc2

am57xx-beagle-x15-revc and its derivatives have 3.3V connected to the
eMMC I/O lines. Also, the MMC core uses both MM_CAP_1_8_V_DDR and
MMC_CAP_3_3V_DDR as an indicator that the host supports DDR52 speed
mode.

Since commit c16bc9a7678a ("mmc: sdhci: Disable 1.8v modes
(HS200/HS400/UHS) if controller can't support 1.8v"), a "no-1-8v"
dt property disables MMC_CAP_1_8V_DDR. Also since commit 3f4028780287
("mmc: sdhci-omap: Get IODelay values for 3.3v DDR mode") the absence of
a pinmux entry of ddr_3_3v disables MMC_CAP_3_3V_DDR in sdhci-omap
driver. Because of these two changes, the device was coming up in high
speed mode instead of DDR52 mode.

Fix the above by replacing ddr_1_8v with ddr_3_3v in the mmc2 pinmux.

Fixes: c16bc9a7678a ("mmc: sdhci: Disable 1.8v modes (HS200/HS400/UHS)
if controller can't support 1.8v"), a "no-1-8v"
Fixes: 3f4028780287 ("mmc: sdhci-omap: Get IODelay values for 3.3v DDR
mode")
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

arch/arm/boot/dts/am57xx-beagle-x15-revc.dts

@@ -32,7 +32,7 @@
 };
 
 &mmc2 {
-	pinctrl-names = "default", "hs", "ddr_1_8v";
+	pinctrl-names = "default", "hs", "ddr_3_3v";
 	pinctrl-0 = <&mmc2_pins_default>;
 	pinctrl-1 = <&mmc2_pins_hs>;
 	pinctrl-2 = <&mmc2_pins_ddr_rev20>;