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@@ -1401,24 +1401,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
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{ 0 },
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};
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-static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
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- { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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- { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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- { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
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- { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
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- { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
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- { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
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- { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
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- { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
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- { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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- { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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- { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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- { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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- { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
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- { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
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- { 0 },
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-};
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-
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#define E4412_CPU_DIV1(cores, hpm, copy) \
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(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
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@@ -1533,17 +1515,10 @@ static void __init exynos4_clk_init(struct device_node *np,
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samsung_clk_register_fixed_factor(ctx,
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exynos4x12_fixed_factor_clks,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
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- if (of_machine_is_compatible("samsung,exynos4412")) {
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- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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- mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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- e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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- CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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- } else {
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- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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- mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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- e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
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- CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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- }
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+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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+ e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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}
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samsung_clk_register_alias(ctx, exynos4_aliases,
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