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@@ -0,0 +1,23 @@
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+Freescale L2 Cache Controller
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+
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+L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
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+The cache bindings explained below are ePAPR compliant
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+
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+Required Properties:
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+
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+- compatible : Should include "fsl,chip-l2-cache-controller" and "cache"
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+ where chip is the processor (bsc9132, npc8572 etc.)
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+- reg : Address and size of L2 cache controller registers
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+- cache-size : Size of the entire L2 cache
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+- interrupts : Error interrupt of L2 controller
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+- cache-line-size : Size of L2 cache lines
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+
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+Example:
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+
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+ L2: l2-cache-controller@20000 {
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+ compatible = "fsl,bsc9132-l2-cache-controller", "cache";
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+ reg = <0x20000 0x1000>;
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+ cache-line-size = <32>; // 32 bytes
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+ cache-size = <0x40000>; // L2,256K
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+ interrupts = <16 2 1 0>;
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+ };
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