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@@ -14,6 +14,7 @@
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/reset-controller/mt8173-resets.h>
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#include "mt8173-pinfunc.h"
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@@ -411,6 +412,37 @@
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#size-cells = <0>;
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status = "disabled";
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};
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+
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+ afe: audio-controller@11220000 {
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+ compatible = "mediatek,mt8173-afe-pcm";
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+ reg = <0 0x11220000 0 0x1000>;
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+ interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
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+ clocks = <&infracfg CLK_INFRA_AUDIO>,
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+ <&topckgen CLK_TOP_AUDIO_SEL>,
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+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
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+ <&topckgen CLK_TOP_APLL1_DIV0>,
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+ <&topckgen CLK_TOP_APLL2_DIV0>,
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+ <&topckgen CLK_TOP_I2S0_M_SEL>,
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+ <&topckgen CLK_TOP_I2S1_M_SEL>,
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+ <&topckgen CLK_TOP_I2S2_M_SEL>,
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+ <&topckgen CLK_TOP_I2S3_M_SEL>,
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+ <&topckgen CLK_TOP_I2S3_B_SEL>;
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+ clock-names = "infra_sys_audio_clk",
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+ "top_pdn_audio",
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+ "top_pdn_aud_intbus",
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+ "bck0",
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+ "bck1",
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+ "i2s0_m",
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+ "i2s1_m",
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+ "i2s2_m",
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+ "i2s3_m",
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+ "i2s3_b";
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+ assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
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+ <&topckgen CLK_TOP_AUD_2_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
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+ <&topckgen CLK_TOP_APLL2>;
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+ };
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};
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};
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