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@@ -4135,7 +4135,10 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
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&msr_info->data);
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case MSR_IA32_XSS:
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- if (!vmx_xsaves_supported())
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+ if (!vmx_xsaves_supported() ||
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+ (!msr_info->host_initiated &&
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+ !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
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+ guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
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return 1;
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msr_info->data = vcpu->arch.ia32_xss;
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break;
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@@ -4302,7 +4305,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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return vmx_set_vmx_msr(vcpu, msr_index, data);
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case MSR_IA32_XSS:
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- if (!vmx_xsaves_supported())
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+ if (!vmx_xsaves_supported() ||
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+ (!msr_info->host_initiated &&
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+ !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
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+ guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
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return 1;
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/*
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* The only supported bit as of Skylake is bit 8, but
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