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@@ -34,7 +34,8 @@
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#define XSPI_CR_MASTER_MODE 0x04
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#define XSPI_CR_MASTER_MODE 0x04
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#define XSPI_CR_CPOL 0x08
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#define XSPI_CR_CPOL 0x08
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#define XSPI_CR_CPHA 0x10
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#define XSPI_CR_CPHA 0x10
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-#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
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+#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
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+ XSPI_CR_LSB_FIRST)
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#define XSPI_CR_TXFIFO_RESET 0x20
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#define XSPI_CR_TXFIFO_RESET 0x20
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#define XSPI_CR_RXFIFO_RESET 0x40
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#define XSPI_CR_RXFIFO_RESET 0x40
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#define XSPI_CR_MANUAL_SSELECT 0x80
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#define XSPI_CR_MANUAL_SSELECT 0x80
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@@ -194,6 +195,8 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
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cr |= XSPI_CR_CPHA;
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cr |= XSPI_CR_CPHA;
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if (spi->mode & SPI_CPOL)
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if (spi->mode & SPI_CPOL)
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cr |= XSPI_CR_CPOL;
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cr |= XSPI_CR_CPOL;
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+ if (spi->mode & SPI_LSB_FIRST)
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+ cr |= XSPI_CR_LSB_FIRST;
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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/* We do not check spi->max_speed_hz here as the SPI clock
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/* We do not check spi->max_speed_hz here as the SPI clock
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@@ -353,7 +356,7 @@ static int xilinx_spi_probe(struct platform_device *pdev)
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return -ENODEV;
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return -ENODEV;
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/* the spi->mode bits understood by this driver: */
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/* the spi->mode bits understood by this driver: */
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- master->mode_bits = SPI_CPOL | SPI_CPHA;
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+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
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xspi = spi_master_get_devdata(master);
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xspi = spi_master_get_devdata(master);
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xspi->bitbang.master = master;
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xspi->bitbang.master = master;
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