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@@ -491,6 +491,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_NUM_EVICTIONS 0x18
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/* Query memory about VRAM and GTT domains */
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#define AMDGPU_INFO_MEMORY 0x19
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+/* Query vce clock table */
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+#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@@ -677,6 +679,24 @@ struct drm_amdgpu_info_hw_ip {
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__u32 _pad;
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};
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+#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
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+
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+struct drm_amdgpu_info_vce_clock_table_entry {
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+ /** System clock */
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+ __u32 sclk;
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+ /** Memory clock */
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+ __u32 mclk;
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+ /** VCE clock */
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+ __u32 eclk;
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+ __u32 pad;
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+};
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+
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+struct drm_amdgpu_info_vce_clock_table {
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+ struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
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+ __u32 num_valid_entries;
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+ __u32 pad;
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+};
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+
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/*
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* Supported GPU families
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*/
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