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@@ -27,27 +27,52 @@ Optional properties:
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- dmas: Should contain dma specifiers for transmit and receive channels
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- dma-names: Should contain "tx" for transmit and "rx" for receive channels
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+Note: Aliases may be defined to ensure the correct ordering of the UARTs.
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+The alias serialN will result in the UART being assigned port N. If any
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+serialN alias exists, then an alias must exist for each enabled UART. The
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+serialN aliases should be in a .dts file instead of in a .dtsi file.
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+
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Examples:
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-A uartdm v1.4 device with dma capabilities.
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-
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-serial@f991e000 {
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- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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- reg = <0xf991e000 0x1000>;
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- interrupts = <0 108 0x0>;
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- clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
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- clock-names = "core", "iface";
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- dmas = <&dma0 0>, <&dma0 1>;
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- dma-names = "tx", "rx";
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-};
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-
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-A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
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-
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-serial@19c40000 {
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- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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- reg = <0x19c40000 0x1000>,
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- <0x19c00000 0x1000>;
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- interrupts = <0 195 0x0>;
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- clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
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- clock-names = "core", "iface";
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-};
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+- A uartdm v1.4 device with dma capabilities.
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+
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+ serial@f991e000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0xf991e000 0x1000>;
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+ interrupts = <0 108 0x0>;
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+ clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
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+ clock-names = "core", "iface";
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+ dmas = <&dma0 0>, <&dma0 1>;
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+ dma-names = "tx", "rx";
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+ };
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+
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+- A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
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+
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+ serial@19c40000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x19c40000 0x1000>,
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+ <0x19c00000 0x1000>;
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+ interrupts = <0 195 0x0>;
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+ clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
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+ clock-names = "core", "iface";
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+ };
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+
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+- serialN alias.
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+
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+ aliases {
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+ serial0 = &uarta;
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+ serial1 = &uartc;
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+ serial2 = &uartb;
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+ };
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+
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+ uarta: serial@12490000 {
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+ status = "ok";
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+ };
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+
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+ uartb: serial@16340000 {
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+ status = "ok";
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+ };
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+
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+ uartc: serial@1a240000 {
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+ status = "ok";
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+ };
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