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@@ -164,6 +164,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
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L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
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L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
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}
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}
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+ WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
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tmp = mmVM_L2_CNTL4_DEFAULT;
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tmp = mmVM_L2_CNTL4_DEFAULT;
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
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