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@@ -661,6 +661,16 @@ static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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return index ? 0 : 100;
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}
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+static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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+{
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+ /*
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+ * SKL doesn't need us to program the AUX clock divider (Hardware will
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+ * derive the clock from CDCLK automatically). We still implement the
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+ * get_aux_clock_divider vfunc to plug-in into the existing code.
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+ */
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+ return index ? 0 : 1;
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+}
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+
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static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
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bool has_aux_irq,
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int send_bytes,
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@@ -5083,7 +5093,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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intel_dp->pps_pipe = INVALID_PIPE;
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/* intel_dp vfuncs */
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- if (IS_VALLEYVIEW(dev))
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+ if (INTEL_INFO(dev)->gen >= 9)
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+ intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
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+ else if (IS_VALLEYVIEW(dev))
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intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
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else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
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