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@@ -75,6 +75,20 @@ static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
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}
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}
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}
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}
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+static int vgic_mmio_uaccess_write_v2_misc(struct kvm_vcpu *vcpu,
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+ gpa_t addr, unsigned int len,
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+ unsigned long val)
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+{
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+ switch (addr & 0x0c) {
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+ case GIC_DIST_IIDR:
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+ if (val != vgic_mmio_read_v2_misc(vcpu, addr, len))
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+ return -EINVAL;
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+ }
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+
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+ vgic_mmio_write_v2_misc(vcpu, addr, len, val);
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+ return 0;
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+}
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+
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static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
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static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
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gpa_t addr, unsigned int len,
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gpa_t addr, unsigned int len,
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unsigned long val)
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unsigned long val)
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@@ -367,9 +381,10 @@ static void vgic_mmio_write_apr(struct kvm_vcpu *vcpu,
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}
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}
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static const struct vgic_register_region vgic_v2_dist_registers[] = {
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static const struct vgic_register_region vgic_v2_dist_registers[] = {
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- REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
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- vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
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- VGIC_ACCESS_32bit),
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+ REGISTER_DESC_WITH_LENGTH_UACCESS(GIC_DIST_CTRL,
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+ vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc,
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+ NULL, vgic_mmio_uaccess_write_v2_misc,
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+ 12, VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
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vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
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vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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VGIC_ACCESS_32bit),
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