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@@ -159,6 +159,8 @@ struct tegra_xusb_soc {
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unsigned int count;
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unsigned int count;
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} usb2, ulpi, hsic, usb3;
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} usb2, ulpi, hsic, usb3;
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} ports;
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} ports;
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+
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+ bool scale_ss_clock;
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};
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};
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struct tegra_xusb {
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struct tegra_xusb {
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@@ -497,13 +499,19 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
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case MBOX_CMD_INC_SSPI_CLOCK:
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case MBOX_CMD_INC_SSPI_CLOCK:
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case MBOX_CMD_DEC_SSPI_CLOCK:
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case MBOX_CMD_DEC_SSPI_CLOCK:
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- err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
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- if (err < 0)
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- rsp.cmd = MBOX_CMD_NAK;
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- else
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+ if (tegra->soc->scale_ss_clock) {
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+ err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
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+ if (err < 0)
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+ rsp.cmd = MBOX_CMD_NAK;
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+ else
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+ rsp.cmd = MBOX_CMD_ACK;
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+
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+ rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
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+ } else {
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rsp.cmd = MBOX_CMD_ACK;
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rsp.cmd = MBOX_CMD_ACK;
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+ rsp.data = msg->data;
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+ }
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- rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
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break;
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break;
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case MBOX_CMD_SET_BW:
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case MBOX_CMD_SET_BW:
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@@ -685,9 +693,11 @@ static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
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if (err < 0)
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if (err < 0)
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goto disable_fs_src;
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goto disable_fs_src;
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- err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
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- if (err < 0)
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- goto disable_hs_src;
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+ if (tegra->soc->scale_ss_clock) {
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+ err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
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+ if (err < 0)
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+ goto disable_hs_src;
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+ }
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return 0;
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return 0;
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@@ -1235,11 +1245,44 @@ static const struct tegra_xusb_soc tegra124_soc = {
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.hsic = { .offset = 6, .count = 2, },
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.hsic = { .offset = 6, .count = 2, },
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.usb3 = { .offset = 0, .count = 2, },
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.usb3 = { .offset = 0, .count = 2, },
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},
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},
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+ .scale_ss_clock = true,
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};
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};
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MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
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MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
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+static const char * const tegra210_supply_names[] = {
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+ "dvddio-pex",
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+ "hvddio-pex",
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+ "avdd-usb",
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+ "avdd-pll-utmip",
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+ "avdd-pll-uerefe",
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+ "dvdd-pex-pll",
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+ "hvdd-pex-pll-e",
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+};
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+
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+static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
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+ { .name = "usb3", .num = 4, },
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+ { .name = "usb2", .num = 4, },
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+ { .name = "hsic", .num = 1, },
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+};
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+
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+static const struct tegra_xusb_soc tegra210_soc = {
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+ .firmware = "nvidia/tegra210/xusb.bin",
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+ .supply_names = tegra210_supply_names,
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+ .num_supplies = ARRAY_SIZE(tegra210_supply_names),
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+ .phy_types = tegra210_phy_types,
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+ .num_types = ARRAY_SIZE(tegra210_phy_types),
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+ .ports = {
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+ .usb2 = { .offset = 4, .count = 4, },
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+ .hsic = { .offset = 8, .count = 1, },
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+ .usb3 = { .offset = 0, .count = 4, },
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+ },
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+ .scale_ss_clock = false,
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+};
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+MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
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+
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static const struct of_device_id tegra_xusb_of_match[] = {
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static const struct of_device_id tegra_xusb_of_match[] = {
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{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
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{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
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+ { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
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{ },
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{ },
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};
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};
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MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
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MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
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