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@@ -562,43 +562,6 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
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*p = calcp;
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}
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-/**
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- * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
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- */
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-
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-void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
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-{
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- #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
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- #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
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-
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- struct clk_hw *hw = __clk_get_hw(clk);
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- struct clk_composite *composite = to_clk_composite(hw);
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- struct clk_hw *rate_hw = composite->rate_hw;
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- struct clk_factors *factors = to_clk_factors(rate_hw);
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- unsigned long flags = 0;
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- u32 reg;
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-
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- if (factors->lock)
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- spin_lock_irqsave(factors->lock, flags);
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-
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- reg = readl(factors->reg);
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-
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- /* set sample clock phase control */
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- reg &= ~(0x7 << 20);
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- reg |= ((sample & 0x7) << 20);
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-
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- /* set output clock phase control */
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- reg &= ~(0x7 << 8);
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- reg |= ((output & 0x7) << 8);
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-
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- writel(reg, factors->reg);
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-
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- if (factors->lock)
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- spin_unlock_irqrestore(factors->lock, flags);
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-}
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-EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
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-
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-
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/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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