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@@ -680,6 +680,25 @@ void aac_set_intx_mode(struct aac_dev *dev)
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}
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}
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+static void aac_clear_omr(struct aac_dev *dev)
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+{
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+ u32 omr_value = 0;
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+
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+ omr_value = src_readl(dev, MUnit.OMR);
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+
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+ /*
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+ * Check for PCI Errors or Kernel Panic
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+ */
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+ if ((omr_value == INVALID_OMR) || (omr_value & KERNEL_PANIC))
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+ omr_value = 0;
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+
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+ /*
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+ * Preserve MSIX Value if any
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+ */
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+ src_writel(dev, MUnit.OMR, omr_value & AAC_INT_MODE_MSIX);
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+ src_readl(dev, MUnit.OMR);
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+}
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+
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static void aac_dump_fw_fib_iop_reset(struct aac_dev *dev)
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{
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__le32 supported_options3;
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@@ -740,6 +759,8 @@ static void aac_send_iop_reset(struct aac_dev *dev)
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aac_set_intx_mode(dev);
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+ aac_clear_omr(dev);
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+
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src_writel(dev, MUnit.IDR, IOP_SRC_RESET_MASK);
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msleep(5000);
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@@ -749,6 +770,7 @@ static void aac_send_hardware_soft_reset(struct aac_dev *dev)
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{
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u_int32_t val;
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+ aac_clear_omr(dev);
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val = readl(((char *)(dev->base) + IBW_SWR_OFFSET));
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val |= 0x01;
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writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET));
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