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@@ -1,13 +1,16 @@
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-PRU Core on TI SoCs
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-===================
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+PRU/RTU Core on TI SoCs
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+=======================
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Each PRUSS has dual PRU cores, each represented by a PRU node. Each PRU core
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has a dedicated Instruction RAM, Control and Debug register sets, and use
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-the Data RAMs present within the PRUSS for code execution.
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+the Data RAMs present within the PRUSS for code execution. K3 SoCs have two
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+additional PRU cores called RTUs with slightly different IP integration. Each
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+RTU core can be used independently like a PRU, or alongside a corresponding
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+PRU core to provide/implement auxiliary functionality/support.
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-Each PRU core node should be defined as a child node of the corresponding PRUSS
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-node. Each node can optionally be rendered inactive by using the standard DT
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-string property, "status".
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+Each PRU or RTU core node should be defined as a child node of the corresponding
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+PRUSS node. Each node can optionally be rendered inactive by using the standard
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+DT string property, "status".
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Please see the overall PRUSS bindings document for additional details
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including a complete example,
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@@ -20,6 +23,8 @@ Required Properties:
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"ti,am4376-pru" for AM437x family of SoCs
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"ti,am5728-pru" for AM57xx family of SoCs
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"ti,k2g-pru" for 66AK2G family of SoCs
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+ "ti,am654-pru" for PRUs in K3 AM65x family of SoCs
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+ "ti,am654-rtu" for RTUs in K3 AM65x family of SoCs
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- reg : base address and size for each of the 3 sub-module address
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spaces as mentioned in reg-names, and in the same order as
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the reg-names
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@@ -72,7 +77,7 @@ devices, so below are in addition to each node's bindings.
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Required Properties:
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--------------------
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-- prus : phandles to the PRU nodes used
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+- prus : phandles to the PRU or RTU nodes used
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Optional Properties:
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--------------------
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