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@@ -68,6 +68,52 @@ void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
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complete(&common->free);
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}
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+static u64 qp_allowed_event_types(void)
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+{
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+ u64 mask;
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+
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+ mask = BIT(MLX5_EVENT_TYPE_PATH_MIG) |
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+ BIT(MLX5_EVENT_TYPE_COMM_EST) |
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+ BIT(MLX5_EVENT_TYPE_SQ_DRAINED) |
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+ BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
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+ BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR) |
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+ BIT(MLX5_EVENT_TYPE_PATH_MIG_FAILED) |
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+ BIT(MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) |
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+ BIT(MLX5_EVENT_TYPE_WQ_ACCESS_ERROR);
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+
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+ return mask;
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+}
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+
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+static u64 rq_allowed_event_types(void)
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+{
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+ u64 mask;
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+
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+ mask = BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
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+ BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
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+
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+ return mask;
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+}
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+
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+static u64 sq_allowed_event_types(void)
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+{
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+ return BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
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+}
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+
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+static bool is_event_type_allowed(int rsc_type, int event_type)
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+{
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+ switch (rsc_type) {
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+ case MLX5_EVENT_QUEUE_TYPE_QP:
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+ return BIT(event_type) & qp_allowed_event_types();
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+ case MLX5_EVENT_QUEUE_TYPE_RQ:
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+ return BIT(event_type) & rq_allowed_event_types();
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+ case MLX5_EVENT_QUEUE_TYPE_SQ:
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+ return BIT(event_type) & sq_allowed_event_types();
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+ default:
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+ WARN(1, "Event arrived for unknown resource type");
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+ return false;
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+ }
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+}
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+
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void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
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{
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struct mlx5_core_rsc_common *common = mlx5_get_rsc(dev, rsn);
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@@ -76,6 +122,12 @@ void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
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if (!common)
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return;
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+ if (!is_event_type_allowed((rsn >> MLX5_USER_INDEX_LEN), event_type)) {
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+ mlx5_core_warn(dev, "event 0x%.2x is not allowed on resource 0x%.8x\n",
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+ event_type, rsn);
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+ return;
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+ }
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+
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switch (common->res) {
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case MLX5_RES_QP:
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case MLX5_RES_RQ:
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