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@@ -253,6 +253,9 @@
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#define STRTAB_STE_1_STRW_EL2 2UL
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#define STRTAB_STE_1_STRW_EL2 2UL
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#define STRTAB_STE_1_STRW_SHIFT 30
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#define STRTAB_STE_1_STRW_SHIFT 30
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+#define STRTAB_STE_1_SHCFG_INCOMING 1UL
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+#define STRTAB_STE_1_SHCFG_SHIFT 44
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+
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#define STRTAB_STE_2_S2VMID_SHIFT 0
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#define STRTAB_STE_2_S2VMID_SHIFT 0
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#define STRTAB_STE_2_S2VMID_MASK 0xffffUL
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#define STRTAB_STE_2_S2VMID_MASK 0xffffUL
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#define STRTAB_STE_2_VTCR_SHIFT 32
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#define STRTAB_STE_2_VTCR_SHIFT 32
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@@ -1041,6 +1044,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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val |= disable_bypass ? STRTAB_STE_0_CFG_ABORT
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val |= disable_bypass ? STRTAB_STE_0_CFG_ABORT
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: STRTAB_STE_0_CFG_BYPASS;
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: STRTAB_STE_0_CFG_BYPASS;
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dst[0] = cpu_to_le64(val);
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dst[0] = cpu_to_le64(val);
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+ dst[1] = cpu_to_le64(STRTAB_STE_1_SHCFG_INCOMING
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+ << STRTAB_STE_1_SHCFG_SHIFT);
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dst[2] = 0; /* Nuke the VMID */
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dst[2] = 0; /* Nuke the VMID */
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if (ste_live)
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if (ste_live)
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arm_smmu_sync_ste_for_sid(smmu, sid);
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arm_smmu_sync_ste_for_sid(smmu, sid);
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