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@@ -35,6 +35,8 @@
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#include <net/mac802154.h>
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#include <net/cfg802154.h>
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+#include "at86rf230.h"
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+
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struct at86rf230_local;
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/* at86rf2xx chip depend data.
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* All timings are in us.
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@@ -50,7 +52,7 @@ struct at86rf2xx_chip_data {
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int rssi_base_val;
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int (*set_channel)(struct at86rf230_local *, u8, u8);
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- int (*get_desense_steps)(struct at86rf230_local *, s32);
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+ int (*set_txpower)(struct at86rf230_local *, s32);
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};
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#define AT86RF2XX_MAX_BUF (127 + 3)
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@@ -102,200 +104,6 @@ struct at86rf230_local {
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struct at86rf230_state_change tx;
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};
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-#define RG_TRX_STATUS (0x01)
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-#define SR_TRX_STATUS 0x01, 0x1f, 0
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-#define SR_RESERVED_01_3 0x01, 0x20, 5
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-#define SR_CCA_STATUS 0x01, 0x40, 6
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-#define SR_CCA_DONE 0x01, 0x80, 7
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-#define RG_TRX_STATE (0x02)
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-#define SR_TRX_CMD 0x02, 0x1f, 0
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-#define SR_TRAC_STATUS 0x02, 0xe0, 5
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-#define RG_TRX_CTRL_0 (0x03)
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-#define SR_CLKM_CTRL 0x03, 0x07, 0
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-#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
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-#define SR_PAD_IO_CLKM 0x03, 0x30, 4
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-#define SR_PAD_IO 0x03, 0xc0, 6
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-#define RG_TRX_CTRL_1 (0x04)
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-#define SR_IRQ_POLARITY 0x04, 0x01, 0
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-#define SR_IRQ_MASK_MODE 0x04, 0x02, 1
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-#define SR_SPI_CMD_MODE 0x04, 0x0c, 2
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-#define SR_RX_BL_CTRL 0x04, 0x10, 4
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-#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
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-#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
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-#define SR_PA_EXT_EN 0x04, 0x80, 7
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-#define RG_PHY_TX_PWR (0x05)
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-#define SR_TX_PWR 0x05, 0x0f, 0
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-#define SR_PA_LT 0x05, 0x30, 4
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-#define SR_PA_BUF_LT 0x05, 0xc0, 6
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-#define RG_PHY_RSSI (0x06)
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-#define SR_RSSI 0x06, 0x1f, 0
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-#define SR_RND_VALUE 0x06, 0x60, 5
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-#define SR_RX_CRC_VALID 0x06, 0x80, 7
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-#define RG_PHY_ED_LEVEL (0x07)
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-#define SR_ED_LEVEL 0x07, 0xff, 0
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-#define RG_PHY_CC_CCA (0x08)
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-#define SR_CHANNEL 0x08, 0x1f, 0
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-#define SR_CCA_MODE 0x08, 0x60, 5
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-#define SR_CCA_REQUEST 0x08, 0x80, 7
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-#define RG_CCA_THRES (0x09)
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-#define SR_CCA_ED_THRES 0x09, 0x0f, 0
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-#define SR_RESERVED_09_1 0x09, 0xf0, 4
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-#define RG_RX_CTRL (0x0a)
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-#define SR_PDT_THRES 0x0a, 0x0f, 0
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-#define SR_RESERVED_0a_1 0x0a, 0xf0, 4
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-#define RG_SFD_VALUE (0x0b)
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-#define SR_SFD_VALUE 0x0b, 0xff, 0
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-#define RG_TRX_CTRL_2 (0x0c)
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-#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
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-#define SR_SUB_MODE 0x0c, 0x04, 2
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-#define SR_BPSK_QPSK 0x0c, 0x08, 3
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-#define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
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-#define SR_RESERVED_0c_5 0x0c, 0x60, 5
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-#define SR_RX_SAFE_MODE 0x0c, 0x80, 7
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-#define RG_ANT_DIV (0x0d)
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-#define SR_ANT_CTRL 0x0d, 0x03, 0
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-#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
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-#define SR_ANT_DIV_EN 0x0d, 0x08, 3
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-#define SR_RESERVED_0d_2 0x0d, 0x70, 4
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-#define SR_ANT_SEL 0x0d, 0x80, 7
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-#define RG_IRQ_MASK (0x0e)
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-#define SR_IRQ_MASK 0x0e, 0xff, 0
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-#define RG_IRQ_STATUS (0x0f)
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-#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
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-#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
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-#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
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-#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
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-#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
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-#define SR_IRQ_5_AMI 0x0f, 0x20, 5
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-#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
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-#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
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-#define RG_VREG_CTRL (0x10)
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-#define SR_RESERVED_10_6 0x10, 0x03, 0
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-#define SR_DVDD_OK 0x10, 0x04, 2
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-#define SR_DVREG_EXT 0x10, 0x08, 3
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-#define SR_RESERVED_10_3 0x10, 0x30, 4
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-#define SR_AVDD_OK 0x10, 0x40, 6
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-#define SR_AVREG_EXT 0x10, 0x80, 7
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-#define RG_BATMON (0x11)
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-#define SR_BATMON_VTH 0x11, 0x0f, 0
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-#define SR_BATMON_HR 0x11, 0x10, 4
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-#define SR_BATMON_OK 0x11, 0x20, 5
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-#define SR_RESERVED_11_1 0x11, 0xc0, 6
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-#define RG_XOSC_CTRL (0x12)
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-#define SR_XTAL_TRIM 0x12, 0x0f, 0
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-#define SR_XTAL_MODE 0x12, 0xf0, 4
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-#define RG_RX_SYN (0x15)
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-#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
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-#define SR_RESERVED_15_2 0x15, 0x70, 4
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-#define SR_RX_PDT_DIS 0x15, 0x80, 7
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-#define RG_XAH_CTRL_1 (0x17)
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-#define SR_RESERVED_17_8 0x17, 0x01, 0
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-#define SR_AACK_PROM_MODE 0x17, 0x02, 1
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-#define SR_AACK_ACK_TIME 0x17, 0x04, 2
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-#define SR_RESERVED_17_5 0x17, 0x08, 3
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-#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
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-#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
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-#define SR_CSMA_LBT_MODE 0x17, 0x40, 6
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-#define SR_RESERVED_17_1 0x17, 0x80, 7
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-#define RG_FTN_CTRL (0x18)
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-#define SR_RESERVED_18_2 0x18, 0x7f, 0
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-#define SR_FTN_START 0x18, 0x80, 7
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-#define RG_PLL_CF (0x1a)
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-#define SR_RESERVED_1a_2 0x1a, 0x7f, 0
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-#define SR_PLL_CF_START 0x1a, 0x80, 7
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-#define RG_PLL_DCU (0x1b)
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-#define SR_RESERVED_1b_3 0x1b, 0x3f, 0
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-#define SR_RESERVED_1b_2 0x1b, 0x40, 6
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-#define SR_PLL_DCU_START 0x1b, 0x80, 7
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-#define RG_PART_NUM (0x1c)
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-#define SR_PART_NUM 0x1c, 0xff, 0
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-#define RG_VERSION_NUM (0x1d)
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-#define SR_VERSION_NUM 0x1d, 0xff, 0
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-#define RG_MAN_ID_0 (0x1e)
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-#define SR_MAN_ID_0 0x1e, 0xff, 0
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-#define RG_MAN_ID_1 (0x1f)
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-#define SR_MAN_ID_1 0x1f, 0xff, 0
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-#define RG_SHORT_ADDR_0 (0x20)
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-#define SR_SHORT_ADDR_0 0x20, 0xff, 0
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-#define RG_SHORT_ADDR_1 (0x21)
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-#define SR_SHORT_ADDR_1 0x21, 0xff, 0
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-#define RG_PAN_ID_0 (0x22)
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-#define SR_PAN_ID_0 0x22, 0xff, 0
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-#define RG_PAN_ID_1 (0x23)
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-#define SR_PAN_ID_1 0x23, 0xff, 0
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-#define RG_IEEE_ADDR_0 (0x24)
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-#define SR_IEEE_ADDR_0 0x24, 0xff, 0
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-#define RG_IEEE_ADDR_1 (0x25)
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-#define SR_IEEE_ADDR_1 0x25, 0xff, 0
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-#define RG_IEEE_ADDR_2 (0x26)
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-#define SR_IEEE_ADDR_2 0x26, 0xff, 0
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-#define RG_IEEE_ADDR_3 (0x27)
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-#define SR_IEEE_ADDR_3 0x27, 0xff, 0
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-#define RG_IEEE_ADDR_4 (0x28)
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-#define SR_IEEE_ADDR_4 0x28, 0xff, 0
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-#define RG_IEEE_ADDR_5 (0x29)
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-#define SR_IEEE_ADDR_5 0x29, 0xff, 0
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-#define RG_IEEE_ADDR_6 (0x2a)
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-#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
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-#define RG_IEEE_ADDR_7 (0x2b)
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-#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
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-#define RG_XAH_CTRL_0 (0x2c)
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-#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
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-#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
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-#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
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-#define RG_CSMA_SEED_0 (0x2d)
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-#define SR_CSMA_SEED_0 0x2d, 0xff, 0
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-#define RG_CSMA_SEED_1 (0x2e)
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-#define SR_CSMA_SEED_1 0x2e, 0x07, 0
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-#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
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-#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
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-#define SR_AACK_SET_PD 0x2e, 0x20, 5
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-#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
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-#define RG_CSMA_BE (0x2f)
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-#define SR_MIN_BE 0x2f, 0x0f, 0
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-#define SR_MAX_BE 0x2f, 0xf0, 4
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-
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-#define CMD_REG 0x80
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-#define CMD_REG_MASK 0x3f
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-#define CMD_WRITE 0x40
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-#define CMD_FB 0x20
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-
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-#define IRQ_BAT_LOW (1 << 7)
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-#define IRQ_TRX_UR (1 << 6)
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-#define IRQ_AMI (1 << 5)
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-#define IRQ_CCA_ED (1 << 4)
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-#define IRQ_TRX_END (1 << 3)
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-#define IRQ_RX_START (1 << 2)
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-#define IRQ_PLL_UNL (1 << 1)
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-#define IRQ_PLL_LOCK (1 << 0)
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-
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-#define IRQ_ACTIVE_HIGH 0
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-#define IRQ_ACTIVE_LOW 1
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-
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-#define STATE_P_ON 0x00 /* BUSY */
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-#define STATE_BUSY_RX 0x01
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-#define STATE_BUSY_TX 0x02
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-#define STATE_FORCE_TRX_OFF 0x03
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-#define STATE_FORCE_TX_ON 0x04 /* IDLE */
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-/* 0x05 */ /* INVALID_PARAMETER */
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-#define STATE_RX_ON 0x06
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-/* 0x07 */ /* SUCCESS */
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-#define STATE_TRX_OFF 0x08
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-#define STATE_TX_ON 0x09
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-/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
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-#define STATE_SLEEP 0x0F
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-#define STATE_PREP_DEEP_SLEEP 0x10
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-#define STATE_BUSY_RX_AACK 0x11
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-#define STATE_BUSY_TX_ARET 0x12
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-#define STATE_RX_AACK_ON 0x16
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-#define STATE_TX_ARET_ON 0x19
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-#define STATE_RX_ON_NOCLK 0x1C
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-#define STATE_RX_AACK_ON_NOCLK 0x1D
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-#define STATE_BUSY_RX_AACK_NOCLK 0x1E
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-#define STATE_TRANSITION_IN_PROGRESS 0x1F
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-
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-#define TRX_STATE_MASK (0x1F)
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-
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#define AT86RF2XX_NUMREGS 0x3F
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static void
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@@ -1010,7 +818,7 @@ at86rf230_xmit_start(void *context)
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if (lp->is_tx_from_off) {
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lp->is_tx_from_off = false;
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at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
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- at86rf230_xmit_tx_on,
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+ at86rf230_write_frame,
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false);
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} else {
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at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
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@@ -1076,6 +884,50 @@ at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
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return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
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}
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+#define AT86RF2XX_MAX_ED_LEVELS 0xF
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+static const s32 at86rf23x_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
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+ -9100, -8900, -8700, -8500, -8300, -8100, -7900, -7700, -7500, -7300,
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+ -7100, -6900, -6700, -6500, -6300, -6100,
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+};
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+
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+static const s32 at86rf212_ed_levels_100[AT86RF2XX_MAX_ED_LEVELS + 1] = {
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+ -10000, -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200,
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+ -8000, -7800, -7600, -7400, -7200, -7000,
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+};
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+
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+static const s32 at86rf212_ed_levels_98[AT86RF2XX_MAX_ED_LEVELS + 1] = {
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+ -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000,
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+ -7800, -7600, -7400, -7200, -7000, -6800,
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+};
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+
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+static inline int
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+at86rf212_update_cca_ed_level(struct at86rf230_local *lp, int rssi_base_val)
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+{
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+ unsigned int cca_ed_thres;
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+ int rc;
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+
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+ rc = at86rf230_read_subreg(lp, SR_CCA_ED_THRES, &cca_ed_thres);
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+ if (rc < 0)
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+ return rc;
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+
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+ switch (rssi_base_val) {
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+ case -98:
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+ lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_98;
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+ lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_98);
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+ lp->hw->phy->cca_ed_level = at86rf212_ed_levels_98[cca_ed_thres];
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+ break;
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+ case -100:
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+ lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
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+ lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
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+ lp->hw->phy->cca_ed_level = at86rf212_ed_levels_100[cca_ed_thres];
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+ break;
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+ default:
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+ WARN_ON(1);
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+ }
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+
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+ return 0;
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+}
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+
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static int
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at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
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{
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@@ -1098,6 +950,10 @@ at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
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if (rc < 0)
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return rc;
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+ rc = at86rf212_update_cca_ed_level(lp, lp->data->rssi_base_val);
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+ if (rc < 0)
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+ return rc;
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+
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/* This sets the symbol_duration according frequency on the 212.
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* TODO move this handling while set channel and page in cfg802154.
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* We can do that, this timings are according 802.15.4 standard.
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@@ -1193,23 +1049,56 @@ at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
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return 0;
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}
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+#define AT86RF23X_MAX_TX_POWERS 0xF
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+static const s32 at86rf233_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
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+ 400, 370, 340, 300, 250, 200, 100, 0, -100, -200, -300, -400, -600,
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+ -800, -1200, -1700,
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+};
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+
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+static const s32 at86rf231_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
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+ 300, 280, 230, 180, 130, 70, 0, -100, -200, -300, -400, -500, -700,
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+ -900, -1200, -1700,
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+};
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+
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+#define AT86RF212_MAX_TX_POWERS 0x1F
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+static const s32 at86rf212_powers[AT86RF212_MAX_TX_POWERS + 1] = {
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+ 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
|
|
|
+ -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
|
|
|
+ -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
|
|
|
+};
|
|
|
+
|
|
|
+static int
|
|
|
+at86rf23x_set_txpower(struct at86rf230_local *lp, s32 mbm)
|
|
|
+{
|
|
|
+ u32 i;
|
|
|
+
|
|
|
+ for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
|
|
|
+ if (lp->hw->phy->supported.tx_powers[i] == mbm)
|
|
|
+ return at86rf230_write_subreg(lp, SR_TX_PWR_23X, i);
|
|
|
+ }
|
|
|
+
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+
|
|
|
static int
|
|
|
-at86rf230_set_txpower(struct ieee802154_hw *hw, s8 db)
|
|
|
+at86rf212_set_txpower(struct at86rf230_local *lp, s32 mbm)
|
|
|
{
|
|
|
- struct at86rf230_local *lp = hw->priv;
|
|
|
+ u32 i;
|
|
|
|
|
|
- /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
|
|
|
- * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
|
|
|
- * 0dB.
|
|
|
- * thus, supported values for db range from -26 to 5, for 31dB of
|
|
|
- * reduction to 0dB of reduction.
|
|
|
- */
|
|
|
- if (db > 5 || db < -26)
|
|
|
- return -EINVAL;
|
|
|
+ for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
|
|
|
+ if (lp->hw->phy->supported.tx_powers[i] == mbm)
|
|
|
+ return at86rf230_write_subreg(lp, SR_TX_PWR_212, i);
|
|
|
+ }
|
|
|
|
|
|
- db = -(db - 5);
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+at86rf230_set_txpower(struct ieee802154_hw *hw, s32 mbm)
|
|
|
+{
|
|
|
+ struct at86rf230_local *lp = hw->priv;
|
|
|
|
|
|
- return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db);
|
|
|
+ return lp->data->set_txpower(lp, mbm);
|
|
|
}
|
|
|
|
|
|
static int
|
|
|
@@ -1254,28 +1143,19 @@ at86rf230_set_cca_mode(struct ieee802154_hw *hw,
|
|
|
return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
|
|
|
}
|
|
|
|
|
|
-static int
|
|
|
-at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level)
|
|
|
-{
|
|
|
- return (level - lp->data->rssi_base_val) * 100 / 207;
|
|
|
-}
|
|
|
-
|
|
|
-static int
|
|
|
-at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level)
|
|
|
-{
|
|
|
- return (level - lp->data->rssi_base_val) / 2;
|
|
|
-}
|
|
|
|
|
|
static int
|
|
|
-at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
|
|
|
+at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
|
|
|
{
|
|
|
struct at86rf230_local *lp = hw->priv;
|
|
|
+ u32 i;
|
|
|
|
|
|
- if (level < lp->data->rssi_base_val || level > 30)
|
|
|
- return -EINVAL;
|
|
|
+ for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
|
|
|
+ if (hw->phy->supported.cca_ed_levels[i] == mbm)
|
|
|
+ return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, i);
|
|
|
+ }
|
|
|
|
|
|
- return at86rf230_write_subreg(lp, SR_CCA_ED_THRES,
|
|
|
- lp->data->get_desense_steps(lp, level));
|
|
|
+ return -EINVAL;
|
|
|
}
|
|
|
|
|
|
static int
|
|
|
@@ -1365,7 +1245,7 @@ static struct at86rf2xx_chip_data at86rf233_data = {
|
|
|
.t_p_ack = 545,
|
|
|
.rssi_base_val = -91,
|
|
|
.set_channel = at86rf23x_set_channel,
|
|
|
- .get_desense_steps = at86rf23x_get_desens_steps
|
|
|
+ .set_txpower = at86rf23x_set_txpower,
|
|
|
};
|
|
|
|
|
|
static struct at86rf2xx_chip_data at86rf231_data = {
|
|
|
@@ -1378,7 +1258,7 @@ static struct at86rf2xx_chip_data at86rf231_data = {
|
|
|
.t_p_ack = 545,
|
|
|
.rssi_base_val = -91,
|
|
|
.set_channel = at86rf23x_set_channel,
|
|
|
- .get_desense_steps = at86rf23x_get_desens_steps
|
|
|
+ .set_txpower = at86rf23x_set_txpower,
|
|
|
};
|
|
|
|
|
|
static struct at86rf2xx_chip_data at86rf212_data = {
|
|
|
@@ -1391,7 +1271,7 @@ static struct at86rf2xx_chip_data at86rf212_data = {
|
|
|
.t_p_ack = 545,
|
|
|
.rssi_base_val = -100,
|
|
|
.set_channel = at86rf212_set_channel,
|
|
|
- .get_desense_steps = at86rf212_get_desens_steps
|
|
|
+ .set_txpower = at86rf212_set_txpower,
|
|
|
};
|
|
|
|
|
|
static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
|
|
|
@@ -1564,8 +1444,21 @@ at86rf230_detect_device(struct at86rf230_local *lp)
|
|
|
}
|
|
|
|
|
|
lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK |
|
|
|
- IEEE802154_HW_TXPOWER | IEEE802154_HW_ARET |
|
|
|
- IEEE802154_HW_AFILT | IEEE802154_HW_PROMISCUOUS;
|
|
|
+ IEEE802154_HW_CSMA_PARAMS |
|
|
|
+ IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
|
|
|
+ IEEE802154_HW_PROMISCUOUS;
|
|
|
+
|
|
|
+ lp->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
|
|
|
+ WPAN_PHY_FLAG_CCA_ED_LEVEL |
|
|
|
+ WPAN_PHY_FLAG_CCA_MODE;
|
|
|
+
|
|
|
+ lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
|
|
|
+ BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
|
|
|
+ lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
|
|
|
+ BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
|
|
|
+
|
|
|
+ lp->hw->phy->supported.cca_ed_levels = at86rf23x_ed_levels;
|
|
|
+ lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf23x_ed_levels);
|
|
|
|
|
|
lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
|
|
|
|
|
|
@@ -1573,36 +1466,49 @@ at86rf230_detect_device(struct at86rf230_local *lp)
|
|
|
case 2:
|
|
|
chip = "at86rf230";
|
|
|
rc = -ENOTSUPP;
|
|
|
- break;
|
|
|
+ goto not_supp;
|
|
|
case 3:
|
|
|
chip = "at86rf231";
|
|
|
lp->data = &at86rf231_data;
|
|
|
- lp->hw->phy->channels_supported[0] = 0x7FFF800;
|
|
|
+ lp->hw->phy->supported.channels[0] = 0x7FFF800;
|
|
|
lp->hw->phy->current_channel = 11;
|
|
|
lp->hw->phy->symbol_duration = 16;
|
|
|
+ lp->hw->phy->supported.tx_powers = at86rf231_powers;
|
|
|
+ lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf231_powers);
|
|
|
break;
|
|
|
case 7:
|
|
|
chip = "at86rf212";
|
|
|
lp->data = &at86rf212_data;
|
|
|
lp->hw->flags |= IEEE802154_HW_LBT;
|
|
|
- lp->hw->phy->channels_supported[0] = 0x00007FF;
|
|
|
- lp->hw->phy->channels_supported[2] = 0x00007FF;
|
|
|
+ lp->hw->phy->supported.channels[0] = 0x00007FF;
|
|
|
+ lp->hw->phy->supported.channels[2] = 0x00007FF;
|
|
|
lp->hw->phy->current_channel = 5;
|
|
|
lp->hw->phy->symbol_duration = 25;
|
|
|
+ lp->hw->phy->supported.lbt = NL802154_SUPPORTED_BOOL_BOTH;
|
|
|
+ lp->hw->phy->supported.tx_powers = at86rf212_powers;
|
|
|
+ lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf212_powers);
|
|
|
+ lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
|
|
|
+ lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
|
|
|
break;
|
|
|
case 11:
|
|
|
chip = "at86rf233";
|
|
|
lp->data = &at86rf233_data;
|
|
|
- lp->hw->phy->channels_supported[0] = 0x7FFF800;
|
|
|
+ lp->hw->phy->supported.channels[0] = 0x7FFF800;
|
|
|
lp->hw->phy->current_channel = 13;
|
|
|
lp->hw->phy->symbol_duration = 16;
|
|
|
+ lp->hw->phy->supported.tx_powers = at86rf233_powers;
|
|
|
+ lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf233_powers);
|
|
|
break;
|
|
|
default:
|
|
|
chip = "unknown";
|
|
|
rc = -ENOTSUPP;
|
|
|
- break;
|
|
|
+ goto not_supp;
|
|
|
}
|
|
|
|
|
|
+ lp->hw->phy->cca_ed_level = lp->hw->phy->supported.cca_ed_levels[7];
|
|
|
+ lp->hw->phy->transmit_power = lp->hw->phy->supported.tx_powers[0];
|
|
|
+
|
|
|
+not_supp:
|
|
|
dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
|
|
|
|
|
|
return rc;
|