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@@ -1121,6 +1121,33 @@ static bool fw_type_is_none(void)
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sizeof(LIO_FW_NAME_TYPE_NONE)) == 0;
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}
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+/**
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+ * \brief PCI FLR for each Octeon device.
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+ * @param oct octeon device
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+ */
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+static void octeon_pci_flr(struct octeon_device *oct)
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+{
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+ int rc;
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+
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+ pci_save_state(oct->pci_dev);
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+
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+ pci_cfg_access_lock(oct->pci_dev);
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+
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+ /* Quiesce the device completely */
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+ pci_write_config_word(oct->pci_dev, PCI_COMMAND,
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+ PCI_COMMAND_INTX_DISABLE);
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+
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+ rc = __pci_reset_function_locked(oct->pci_dev);
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+
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+ if (rc != 0)
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+ dev_err(&oct->pci_dev->dev, "Error %d resetting PCI function %d\n",
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+ rc, oct->pf_num);
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+
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+ pci_cfg_access_unlock(oct->pci_dev);
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+
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+ pci_restore_state(oct->pci_dev);
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+}
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+
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/**
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*\brief Destroy resources associated with octeon device
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* @param pdev PCI device structure
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@@ -1269,14 +1296,16 @@ static void octeon_destroy_resources(struct octeon_device *oct)
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case OCT_DEV_PCI_MAP_DONE:
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refcount = octeon_deregister_device(oct);
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- if (!fw_type_is_none()) {
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- /* Soft reset the octeon device before exiting.
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- * Implementation note: here, we reset the device
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- * if it is a CN6XXX OR the last CN23XX device.
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- */
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- if (OCTEON_CN6XXX(oct) || !refcount)
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- oct->fn_list.soft_reset(oct);
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- }
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+ /* Soft reset the octeon device before exiting.
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+ * However, if fw was loaded from card (i.e. autoboot),
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+ * perform an FLR instead.
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+ * Implementation note: only soft-reset the device
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+ * if it is a CN6XXX OR the LAST CN23XX device.
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+ */
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+ if (fw_type_is_none())
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+ octeon_pci_flr(oct);
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+ else if (OCTEON_CN6XXX(oct) || !refcount)
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+ oct->fn_list.soft_reset(oct);
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octeon_unmap_pci_barx(oct, 0);
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octeon_unmap_pci_barx(oct, 1);
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@@ -1912,11 +1941,6 @@ static int load_firmware(struct octeon_device *oct)
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char fw_name[LIO_MAX_FW_FILENAME_LEN];
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char *tmp_fw_type;
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- if (fw_type_is_none()) {
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- dev_info(&oct->pci_dev->dev, "Skipping firmware load\n");
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- return ret;
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- }
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-
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if (fw_type[0] == '\0')
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tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
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else
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@@ -3900,18 +3924,16 @@ static int octeon_device_init(struct octeon_device *octeon_dev)
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octeon_dev->app_mode = CVM_DRV_INVALID_APP;
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if (OCTEON_CN23XX_PF(octeon_dev)) {
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- if (!cn23xx_fw_loaded(octeon_dev)) {
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+ if (!cn23xx_fw_loaded(octeon_dev) && !fw_type_is_none()) {
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fw_loaded = 0;
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- if (!fw_type_is_none()) {
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- /* Do a soft reset of the Octeon device. */
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- if (octeon_dev->fn_list.soft_reset(octeon_dev))
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- return 1;
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- /* things might have changed */
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- if (!cn23xx_fw_loaded(octeon_dev))
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- fw_loaded = 0;
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- else
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- fw_loaded = 1;
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- }
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+ /* Do a soft reset of the Octeon device. */
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+ if (octeon_dev->fn_list.soft_reset(octeon_dev))
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+ return 1;
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+ /* things might have changed */
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+ if (!cn23xx_fw_loaded(octeon_dev))
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+ fw_loaded = 0;
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+ else
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+ fw_loaded = 1;
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} else {
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fw_loaded = 1;
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}
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@@ -4027,6 +4049,18 @@ static int octeon_device_init(struct octeon_device *octeon_dev)
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atomic_set(&octeon_dev->status, OCT_DEV_INTR_SET_DONE);
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+ /* Send Credit for Octeon Output queues. Credits are always sent BEFORE
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+ * the output queue is enabled.
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+ * This ensures that we'll receive the f/w CORE DRV_ACTIVE message in
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+ * case we've configured CN23XX_SLI_GBL_CONTROL[NOPTR_D] = 0.
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+ * Otherwise, it is possible that the DRV_ACTIVE message will be sent
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+ * before any credits have been issued, causing the ring to be reset
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+ * (and the f/w appear to never have started).
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+ */
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+ for (j = 0; j < octeon_dev->num_oqs; j++)
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+ writel(octeon_dev->droq[j]->max_count,
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+ octeon_dev->droq[j]->pkts_credit_reg);
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+
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/* Enable the input and output queues for this Octeon device */
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ret = octeon_dev->fn_list.enable_io_queues(octeon_dev);
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if (ret) {
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@@ -4111,14 +4145,6 @@ static int octeon_device_init(struct octeon_device *octeon_dev)
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atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
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- /* Send Credit for Octeon Output queues. Credits are always sent after
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- * the output queue is enabled.
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- */
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- for (j = 0; j < octeon_dev->num_oqs; j++)
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- writel(octeon_dev->droq[j]->max_count,
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- octeon_dev->droq[j]->pkts_credit_reg);
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-
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- /* Packets can start arriving on the output queues from this point. */
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return 0;
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}
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