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@@ -44,9 +44,10 @@
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#include "skeleton.dtsi"
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-#include <dt-bindings/clock/sun4i-a10-pll2.h>
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+#include <dt-bindings/clock/sun5i-ccu.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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+#include <dt-bindings/reset/sun5i-ccu.h>
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/ {
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interrupt-parent = <&intc>;
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@@ -59,7 +60,7 @@
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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- clocks = <&cpu>;
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+ clocks = <&ccu CLK_CPU>;
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};
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};
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@@ -68,291 +69,19 @@
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#size-cells = <1>;
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ranges;
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- /*
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- * This is a dummy clock, to be used as placeholder on
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- * other mux clocks when a specific parent clock is not
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- * yet implemented. It should be dropped when the driver
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- * is complete.
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- */
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- dummy: dummy {
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- #clock-cells = <0>;
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- compatible = "fixed-clock";
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- clock-frequency = <0>;
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- };
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-
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-osc-clk";
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- reg = <0x01c20050 0x4>;
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+ compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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- osc3M: osc3M_clk {
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- compatible = "fixed-factor-clock";
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- #clock-cells = <0>;
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- clock-div = <8>;
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- clock-mult = <1>;
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- clocks = <&osc24M>;
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- clock-output-names = "osc3M";
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- };
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-
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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-
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- pll1: clk@01c20000 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-pll1-clk";
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- reg = <0x01c20000 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll1";
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- };
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-
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- pll2: clk@01c20008 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun5i-a13-pll2-clk";
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- reg = <0x01c20008 0x8>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll2-1x", "pll2-2x",
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- "pll2-4x", "pll2-8x";
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- };
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-
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- pll3: clk@01c20010 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-pll3-clk";
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- reg = <0x01c20010 0x4>;
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- clocks = <&osc3M>;
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- clock-output-names = "pll3";
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- };
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-
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- pll3x2: pll3x2_clk {
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- compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
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- #clock-cells = <0>;
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- clock-div = <1>;
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- clock-mult = <2>;
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- clocks = <&pll3>;
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- clock-output-names = "pll3-2x";
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- };
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-
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- pll4: clk@01c20018 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-pll1-clk";
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- reg = <0x01c20018 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll4";
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- };
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-
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- pll5: clk@01c20020 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-pll5-clk";
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- reg = <0x01c20020 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll5_ddr", "pll5_other";
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- };
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-
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- pll6: clk@01c20028 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-pll6-clk";
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- reg = <0x01c20028 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll6_sata", "pll6_other", "pll6";
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- };
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-
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- pll7: clk@01c20030 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-pll3-clk";
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- reg = <0x01c20030 0x4>;
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- clocks = <&osc3M>;
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- clock-output-names = "pll7";
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- };
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-
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- pll7x2: pll7x2_clk {
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- compatible = "fixed-factor-clock";
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- #clock-cells = <0>;
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- clock-div = <1>;
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- clock-mult = <2>;
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- clocks = <&pll7>;
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- clock-output-names = "pll7-2x";
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- };
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-
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- /* dummy is 200M */
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- cpu: cpu@01c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-cpu-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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- clock-output-names = "cpu";
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- };
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-
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- axi: axi@01c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-axi-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&cpu>;
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- clock-output-names = "axi";
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- };
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-
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- ahb: ahb@01c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun5i-a13-ahb-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&axi>, <&cpu>, <&pll6 1>;
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- clock-output-names = "ahb";
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- /*
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- * Use PLL6 as parent, instead of CPU/AXI
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- * which has rate changes due to cpufreq
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- */
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- assigned-clocks = <&ahb>;
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- assigned-clock-parents = <&pll6 1>;
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- };
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-
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- apb0: apb0@01c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-apb0-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&ahb>;
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- clock-output-names = "apb0";
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- };
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-
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- apb1: clk@01c20058 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-apb1-clk";
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- reg = <0x01c20058 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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- clock-output-names = "apb1";
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- };
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-
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- axi_gates: clk@01c2005c {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-axi-gates-clk";
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- reg = <0x01c2005c 0x4>;
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- clocks = <&axi>;
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- clock-indices = <0>;
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- clock-output-names = "axi_dram";
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- };
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-
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- nand_clk: clk@01c20080 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c20080 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "nand";
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- };
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-
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- ms_clk: clk@01c20084 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c20084 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "ms";
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- };
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-
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- mmc0_clk: clk@01c20088 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-mmc-clk";
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- reg = <0x01c20088 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "mmc0",
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- "mmc0_output",
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- "mmc0_sample";
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- };
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-
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- mmc1_clk: clk@01c2008c {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-mmc-clk";
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- reg = <0x01c2008c 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "mmc1",
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- "mmc1_output",
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- "mmc1_sample";
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- };
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-
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- mmc2_clk: clk@01c20090 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-mmc-clk";
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- reg = <0x01c20090 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "mmc2",
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- "mmc2_output",
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- "mmc2_sample";
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- };
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-
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- ts_clk: clk@01c20098 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c20098 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "ts";
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- };
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-
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- ss_clk: clk@01c2009c {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c2009c 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "ss";
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- };
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-
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- spi0_clk: clk@01c200a0 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c200a0 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "spi0";
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- };
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-
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- spi1_clk: clk@01c200a4 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c200a4 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "spi1";
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- };
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-
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- spi2_clk: clk@01c200a8 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c200a8 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "spi2";
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- };
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-
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- ir0_clk: clk@01c200b0 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c200b0 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "ir0";
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- };
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-
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- usb_clk: clk@01c200cc {
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- compatible = "allwinner,sun5i-a13-usb-clk";
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- reg = <0x01c200cc 0x4>;
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- clocks = <&pll6 1>;
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- clock-output-names = "usb_ohci0", "usb_phy";
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- };
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-
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- codec_clk: clk@01c20140 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-codec-clk";
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- reg = <0x01c20140 0x4>;
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- clocks = <&pll2 SUN4I_A10_PLL2_1X>;
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- clock-output-names = "codec";
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- };
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-
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- mbus_clk: clk@01c2015c {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun5i-a13-mbus-clk";
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- reg = <0x01c2015c 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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- clock-output-names = "mbus";
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- };
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};
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soc@01c00000 {
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@@ -395,7 +124,7 @@
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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- clocks = <&ahb_gates 6>;
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+ clocks = <&ccu CLK_AHB_DMA>;
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#dma-cells = <2>;
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};
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@@ -403,7 +132,7 @@
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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- clocks = <&ahb_gates 20>, <&spi0_clk>;
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+ clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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@@ -417,7 +146,7 @@
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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- clocks = <&ahb_gates 21>, <&spi1_clk>;
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+ clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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@@ -430,14 +159,8 @@
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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- clocks = <&ahb_gates 8>,
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- <&mmc0_clk 0>,
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- <&mmc0_clk 1>,
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- <&mmc0_clk 2>;
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- clock-names = "ahb",
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- "mmc",
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- "output",
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- "sample";
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+ clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
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+ clock-names = "ahb", "mmc";
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interrupts = <32>;
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status = "disabled";
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#address-cells = <1>;
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@@ -447,14 +170,8 @@
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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- clocks = <&ahb_gates 9>,
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- <&mmc1_clk 0>,
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- <&mmc1_clk 1>,
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- <&mmc1_clk 2>;
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- clock-names = "ahb",
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- "mmc",
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- "output",
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- "sample";
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+ clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
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+ clock-names = "ahb", "mmc";
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interrupts = <33>;
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status = "disabled";
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#address-cells = <1>;
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@@ -464,14 +181,8 @@
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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- clocks = <&ahb_gates 10>,
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- <&mmc2_clk 0>,
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- <&mmc2_clk 1>,
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- <&mmc2_clk 2>;
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- clock-names = "ahb",
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- "mmc",
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- "output",
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- "sample";
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|
|
+ clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
|
|
|
+ clock-names = "ahb", "mmc";
|
|
|
interrupts = <34>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
@@ -481,7 +192,7 @@
|
|
|
usb_otg: usb@01c13000 {
|
|
|
compatible = "allwinner,sun4i-a10-musb";
|
|
|
reg = <0x01c13000 0x0400>;
|
|
|
- clocks = <&ahb_gates 0>;
|
|
|
+ clocks = <&ccu CLK_AHB_OTG>;
|
|
|
interrupts = <38>;
|
|
|
interrupt-names = "mc";
|
|
|
phys = <&usbphy 0>;
|
|
|
@@ -496,9 +207,9 @@
|
|
|
compatible = "allwinner,sun5i-a13-usb-phy";
|
|
|
reg = <0x01c13400 0x10 0x01c14800 0x4>;
|
|
|
reg-names = "phy_ctrl", "pmu1";
|
|
|
- clocks = <&usb_clk 8>;
|
|
|
+ clocks = <&ccu CLK_USB_PHY0>;
|
|
|
clock-names = "usb_phy";
|
|
|
- resets = <&usb_clk 0>, <&usb_clk 1>;
|
|
|
+ resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
|
|
|
reset-names = "usb0_reset", "usb1_reset";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
@@ -507,7 +218,7 @@
|
|
|
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
|
|
|
reg = <0x01c14000 0x100>;
|
|
|
interrupts = <39>;
|
|
|
- clocks = <&ahb_gates 1>;
|
|
|
+ clocks = <&ccu CLK_AHB_EHCI>;
|
|
|
phys = <&usbphy 1>;
|
|
|
phy-names = "usb";
|
|
|
status = "disabled";
|
|
|
@@ -517,7 +228,7 @@
|
|
|
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
|
|
|
reg = <0x01c14400 0x100>;
|
|
|
interrupts = <40>;
|
|
|
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
|
|
+ clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
|
|
|
phys = <&usbphy 1>;
|
|
|
phy-names = "usb";
|
|
|
status = "disabled";
|
|
|
@@ -527,7 +238,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
reg = <0x01c17000 0x1000>;
|
|
|
interrupts = <12>;
|
|
|
- clocks = <&ahb_gates 22>, <&spi2_clk>;
|
|
|
+ clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
|
|
|
clock-names = "ahb", "mod";
|
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
|
|
<&dma SUN4I_DMA_DEDICATED 28>;
|
|
|
@@ -537,6 +248,14 @@
|
|
|
#size-cells = <0>;
|
|
|
};
|
|
|
|
|
|
+ ccu: clock@01c20000 {
|
|
|
+ reg = <0x01c20000 0x400>;
|
|
|
+ clocks = <&osc24M>, <&osc32k>;
|
|
|
+ clock-names = "hosc", "losc";
|
|
|
+ #clock-cells = <1>;
|
|
|
+ #reset-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
intc: interrupt-controller@01c20400 {
|
|
|
compatible = "allwinner,sun4i-a10-ic";
|
|
|
reg = <0x01c20400 0x400>;
|
|
|
@@ -547,7 +266,7 @@
|
|
|
pio: pinctrl@01c20800 {
|
|
|
reg = <0x01c20800 0x400>;
|
|
|
interrupts = <28>;
|
|
|
- clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
|
|
|
+ clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
|
|
clock-names = "apb", "hosc", "losc";
|
|
|
gpio-controller;
|
|
|
interrupt-controller;
|
|
|
@@ -642,7 +361,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
|
reg = <0x01c20c00 0x90>;
|
|
|
interrupts = <22>;
|
|
|
- clocks = <&osc24M>;
|
|
|
+ clocks = <&ccu CLK_HOSC>;
|
|
|
};
|
|
|
|
|
|
wdt: watchdog@01c20c90 {
|
|
|
@@ -662,7 +381,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-codec";
|
|
|
reg = <0x01c22c00 0x40>;
|
|
|
interrupts = <30>;
|
|
|
- clocks = <&apb0_gates 0>, <&codec_clk>;
|
|
|
+ clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
|
|
clock-names = "apb", "codec";
|
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
|
@@ -688,7 +407,7 @@
|
|
|
interrupts = <2>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb1_gates 17>;
|
|
|
+ clocks = <&ccu CLK_APB1_UART1>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
@@ -698,7 +417,7 @@
|
|
|
interrupts = <4>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb1_gates 19>;
|
|
|
+ clocks = <&ccu CLK_APB1_UART3>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
@@ -706,7 +425,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
interrupts = <7>;
|
|
|
- clocks = <&apb1_gates 0>;
|
|
|
+ clocks = <&ccu CLK_APB1_I2C0>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
@@ -716,7 +435,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
interrupts = <8>;
|
|
|
- clocks = <&apb1_gates 1>;
|
|
|
+ clocks = <&ccu CLK_APB1_I2C1>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
@@ -726,7 +445,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
interrupts = <9>;
|
|
|
- clocks = <&apb1_gates 2>;
|
|
|
+ clocks = <&ccu CLK_APB1_I2C2>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
@@ -736,7 +455,7 @@
|
|
|
compatible = "allwinner,sun5i-a13-hstimer";
|
|
|
reg = <0x01c60000 0x1000>;
|
|
|
interrupts = <82>, <83>;
|
|
|
- clocks = <&ahb_gates 28>;
|
|
|
+ clocks = <&ccu CLK_AHB_HSTIMER>;
|
|
|
};
|
|
|
};
|
|
|
};
|
Maxime Ripard