arm64: dts: ti: k3-j721e-main: Add dt for WIZ and SERDES

Add dt node for the three instances of WIZ and SERDES module
used by PCIe.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

@@ -4,6 +4,7 @@
  *
  * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
  */
+#include <dt-bindings/phy/phy.h>
 
 &cbass_main {
 	msmc_ram: sram@70000000 {
@@ -466,6 +467,266 @@
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
+	dummy_cmn_refclk: dummy_cmn_refclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	dummy_cmn_refclk1: dummy_cmn_refclk1 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	serdes_wiz0: wiz@5000000 {
+		compatible = "ti,j721e-wiz";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+		num-lanes = <2>;
+		#reset-cells = <1>;
+		ranges;
+
+		wiz0_pll0_refclk: pll0_refclk {
+			clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz0_pll0_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz0_pll0_refclk>;
+			assigned-clock-parents = <&k3_clks 292 11>;
+		};
+
+		wiz0_pll1_refclk: pll1_refclk {
+			clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz0_pll1_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz0_pll1_refclk>;
+			assigned-clock-parents = <&k3_clks 292 0>;
+		};
+
+		wiz0_refclk_dig: refclk_dig {
+			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz0_refclk_dig";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz0_refclk_dig>;
+			assigned-clock-parents = <&k3_clks 292 11>;
+		};
+
+		wiz0_cmn_refclk: cmn_refclk {
+			clocks = <&wiz0_refclk_dig>;
+			clock-output-names = "wiz0_cmn_refclk";
+			#clock-cells = <0>;
+		};
+
+		wiz0_cmn_refclk1: cmn_refclk1 {
+			clocks = <&wiz0_pll1_refclk>;
+			clock-output-names = "wiz0_cmn_refclk1";
+			#clock-cells = <0>;
+		};
+
+		serdes0: serdes@5000000 {
+			compatible = "cdns,ti,sierra-phy-t0";
+			reg-names = "serdes";
+			reg = <0x00 0x5000000 0x00 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&serdes_wiz0 0>;
+			reset-names = "sierra_reset";
+			clocks = <&wiz0_cmn_refclk>, <&wiz0_cmn_refclk1>;
+			clock-names = "cmn_refclk", "cmn_refclk1";
+		};
+	};
+
+	serdes_wiz1: wiz@5010000 {
+		compatible = "ti,j721e-wiz";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
+		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
+		num-lanes = <2>;
+		#reset-cells = <1>;
+		ranges;
+
+		wiz1_pll0_refclk: pll0_refclk {
+			clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz1_pll0_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz1_pll0_refclk>;
+			assigned-clock-parents = <&k3_clks 293 13>;
+		};
+
+		wiz1_pll1_refclk: pll1_refclk {
+			clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz1_pll1_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz1_pll1_refclk>;
+			assigned-clock-parents = <&k3_clks 293 0>;
+		};
+
+		wiz1_refclk_dig: refclk_dig {
+			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz1_refclk_dig";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz1_refclk_dig>;
+			assigned-clock-parents = <&k3_clks 293 13>;
+		};
+
+		wiz1_cmn_refclk: cmn_refclk {
+			clocks = <&wiz1_refclk_dig>;
+			clock-output-names = "wiz1_cmn_refclk";
+			#clock-cells = <0>;
+		};
+
+		wiz1_cmn_refclk1: cmn_refclk1 {
+			clocks = <&wiz1_pll1_refclk>;
+			clock-output-names = "wiz1_cmn_refclk1";
+			#clock-cells = <0>;
+		};
+
+		serdes1: serdes@5010000 {
+			compatible = "cdns,ti,sierra-phy-t0";
+			reg-names = "serdes";
+			reg = <0x00 0x5010000 0x00 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&serdes_wiz1 0>;
+			reset-names = "sierra_reset";
+			clocks = <&wiz1_cmn_refclk>, <&wiz1_cmn_refclk1>;
+			clock-names = "cmn_refclk", "cmn_refclk1";
+		};
+	};
+
+	serdes_wiz2: wiz@5020000 {
+		compatible = "ti,j721e-wiz";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
+		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
+		num-lanes = <2>;
+		#reset-cells = <1>;
+		ranges;
+
+		wiz2_pll0_refclk: pll0_refclk {
+			clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz2_pll0_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz2_pll0_refclk>;
+			assigned-clock-parents = <&k3_clks 294 11>;
+		};
+
+		wiz2_pll1_refclk: pll1_refclk {
+			clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz2_pll1_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz2_pll1_refclk>;
+			assigned-clock-parents = <&k3_clks 294 0>;
+		};
+
+		wiz2_refclk_dig: refclk_dig {
+			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz2_refclk_dig";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz2_refclk_dig>;
+			assigned-clock-parents = <&k3_clks 294 11>;
+		};
+
+		wiz2_cmn_refclk: cmn_refclk {
+			clocks = <&wiz2_refclk_dig>;
+			clock-output-names = "wiz2_cmn_refclk";
+			#clock-cells = <0>;
+		};
+
+		wiz2_cmn_refclk1: cmn_refclk1 {
+			clocks = <&wiz2_pll1_refclk>;
+			clock-output-names = "wiz2_cmn_refclk1";
+			#clock-cells = <0>;
+		};
+
+		serdes2: serdes@5020000 {
+			compatible = "cdns,ti,sierra-phy-t0";
+			reg-names = "serdes";
+			reg = <0x00 0x5020000 0x00 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&serdes_wiz2 0>;
+			reset-names = "sierra_reset";
+			clocks = <&wiz2_cmn_refclk>, <&wiz2_cmn_refclk1>;
+			clock-names = "cmn_refclk", "cmn_refclk1";
+		};
+	};
+
+	serdes_wiz3: wiz@5030000 {
+		compatible = "ti,j721e-wiz";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
+		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
+		num-lanes = <2>;
+		#reset-cells = <1>;
+		ranges;
+
+		wiz3_pll0_refclk: pll0_refclk {
+			clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+			clock-output-names = "wiz3_pll0_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz3_pll0_refclk>;
+			assigned-clock-parents = <&k3_clks 295 9>;
+		};
+
+		wiz3_pll1_refclk: pll1_refclk {
+			clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz3_pll1_refclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz3_pll1_refclk>;
+			assigned-clock-parents = <&k3_clks 295 0>;
+		};
+
+		wiz3_refclk_dig: refclk_dig {
+			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+			clock-output-names = "wiz3_refclk_dig";
+			#clock-cells = <0>;
+			assigned-clocks = <&wiz3_refclk_dig>;
+			assigned-clock-parents = <&k3_clks 295 9>;
+		};
+
+		wiz3_cmn_refclk: cmn_refclk {
+			clocks = <&wiz3_refclk_dig>;
+			clock-output-names = "wiz3_cmn_refclk";
+			#clock-cells = <0>;
+		};
+
+		wiz3_cmn_refclk1: cmn_refclk1 {
+			clocks = <&wiz3_pll1_refclk>;
+			clock-output-names = "wiz3_cmn_refclk1";
+			#clock-cells = <0>;
+		};
+
+		serdes3: serdes@5030000 {
+			compatible = "cdns,ti,sierra-phy-t0";
+			reg-names = "serdes";
+			reg = <0x00 0x5030000 0x00 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&serdes_wiz3 0>;
+			reset-names = "sierra_reset";
+			clocks = <&wiz3_cmn_refclk>, <&wiz3_cmn_refclk1>;
+			clock-names = "cmn_refclk", "cmn_refclk1";
+		};
+	};
+
 	main_uart0: serial@2800000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
 		reg = <0x00 0x02800000 0x00 0x100>;