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@@ -0,0 +1,627 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * TI PAT mapped DMA-BUF memory re-exporter
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+ *
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+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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+ * Andrew F. Davis <afd@ti.com>
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+ */
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+
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+#include <linux/dma-buf.h>
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+#include <linux/fs.h>
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+#include <linux/genalloc.h>
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+#include <linux/miscdevice.h>
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+#include <linux/module.h>
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+#include <linux/mod_devicetable.h>
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+#include <linux/platform_device.h>
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+#include <linux/property.h>
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+#include <linux/regmap.h>
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+#include <linux/slab.h>
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+#include <linux/uaccess.h>
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+#include <linux/vmalloc.h>
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+
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+#include <linux/ti-pat.h>
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+
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+/* TI PAT MMRS registers */
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+#define TI_PAT_MMRS_PID 0x0 /* Revision Register */
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+#define TI_PAT_MMRS_CONFIG 0x4 /* Config Register */
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+#define TI_PAT_MMRS_CONTROL 0x10 /* Control Register */
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+
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+/* TI PAT CONTROL register field values */
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+#define TI_PAT_CONTROL_ARB_MODE_UF 0x0 /* Updates first */
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+#define TI_PAT_CONTROL_ARB_MODE_RR 0x2 /* Round-robin */
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+
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+#define TI_PAT_CONTROL_PAGE_SIZE_4KB 0x0
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+#define TI_PAT_CONTROL_PAGE_SIZE_16KB 0x1
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+#define TI_PAT_CONTROL_PAGE_SIZE_64KB 0x2
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+#define TI_PAT_CONTROL_PAGE_SIZE_1MB 0x3
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+
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+/* TI PAT TABLE registers */
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+#define TI_PAT_TABLE_ADDRL 0x0 /* Low address Register */
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+#define TI_PAT_TABLE_ADDRH 0x4 /* High address and enable Register */
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+
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+static unsigned int ti_pat_page_sizes[] = {
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+ [TI_PAT_CONTROL_PAGE_SIZE_4KB] = 4 * 1024,
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+ [TI_PAT_CONTROL_PAGE_SIZE_16KB] = 16 * 1024,
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+ [TI_PAT_CONTROL_PAGE_SIZE_64KB] = 64 * 1024,
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+ [TI_PAT_CONTROL_PAGE_SIZE_1MB] = 1024 * 1024,
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+};
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+
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+enum ti_pat_fields {
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+ /* Revision */
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+ F_PID_MAJOR,
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+ F_PID_MINOR,
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+
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+ /* Controls */
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+ F_CONTROL_ARB_MODE,
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+ F_CONTROL_PAGE_SIZE,
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+ F_CONTROL_REPLACE_OID_EN,
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+ F_CONTROL_EN,
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+
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+ /* sentinel */
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+ F_MMRS_FIELDS,
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+
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+ /* Table */
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+ F_TABLE_ADDRL,
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+ F_TABLE_ADDRH,
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+ F_TABLE_ENABLE,
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+
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+ /* sentinel */
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+ F_MAX_FIELDS
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+};
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+
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+static struct reg_field ti_pat_reg_fields[] = {
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+ /* Revision */
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+ [F_PID_MAJOR] = REG_FIELD(TI_PAT_MMRS_PID, 8, 10),
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+ [F_PID_MINOR] = REG_FIELD(TI_PAT_MMRS_PID, 0, 5),
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+ /* Controls */
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+ [F_CONTROL_ARB_MODE] = REG_FIELD(TI_PAT_MMRS_CONTROL, 6, 7),
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+ [F_CONTROL_PAGE_SIZE] = REG_FIELD(TI_PAT_MMRS_CONTROL, 4, 5),
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+ [F_CONTROL_REPLACE_OID_EN] = REG_FIELD(TI_PAT_MMRS_CONTROL, 1, 1),
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+ [F_CONTROL_EN] = REG_FIELD(TI_PAT_MMRS_CONTROL, 0, 0),
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+ /* Table */
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+ [F_TABLE_ADDRL] = REG_FIELD(TI_PAT_TABLE_ADDRL, 0, 31),
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+ [F_TABLE_ADDRH] = REG_FIELD(TI_PAT_TABLE_ADDRH, 0, 3),
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+ [F_TABLE_ENABLE] = REG_FIELD(TI_PAT_TABLE_ADDRH, 31, 31),
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+};
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+
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+/**
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+ * struct ti_pat_data - PAT device instance data
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+ * @dev: PAT device structure
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+ * @mdev: misc device
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+ * @mmrs_fields: Register fields for both MMRS and TABLE
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+ * @page_count: Total number of pages in this PAT
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+ * @page_size: Size of region mapped by each page in bytes
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+ * @window_base: Base address of WINDOW region
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+ * @pool: Pool for managing translation space
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+ */
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+struct ti_pat_data {
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+ struct device *dev;
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+ struct miscdevice mdev;
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+ struct regmap_field *fields[F_MAX_FIELDS];
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+ unsigned int page_count;
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+ unsigned int page_size;
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+ phys_addr_t window_base;
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+ struct gen_pool *pool;
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+};
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+
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+struct ti_pat_dma_buf_attachment {
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+ struct device *dev;
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+ struct sg_table *table;
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+ struct ti_pat_buffer *buffer;
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+ struct list_head list;
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+};
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+
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+/**
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+ * struct ti_pat_buffer - Single buffer instance data
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+ * @pat: PAT instance for whom this buffer belongs
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+ * @i_dma_buf: Imported DMA-BUF buffer
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+ * @size: Total allocated size of this buffer
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+ * @offset: Allocated offset into the PAT window
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+ * @e_dma_buf: Exported DMA-BUF buffer
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+ * @attachment: Our attachment to the imported buffer
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+ * @sgt: DMA map of our imported buffer
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+ * @attachments: Attachments to this buffer
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+ * @map_count: Reference count of mappings to this buffer
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+ * @lock: Protect the attach list and map count
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+ */
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+struct ti_pat_buffer {
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+ struct ti_pat_data *pat;
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+ struct dma_buf *i_dma_buf;
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+ size_t size;
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+ unsigned long offset;
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+ struct dma_buf *e_dma_buf;
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+
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+ struct dma_buf_attachment *attachment;
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+ struct sg_table *sgt;
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+
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+ struct list_head attachments;
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+ int map_count;
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+
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+ struct mutex lock;
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+};
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+
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+static const struct regmap_config ti_pat_regmap_config = {
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+ .reg_bits = 32,
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+ .val_bits = 32,
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+ .reg_stride = 4,
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+};
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+
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+static int ti_pat_dma_buf_attach(struct dma_buf *dmabuf,
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+ struct dma_buf_attachment *attachment)
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+{
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+ struct ti_pat_dma_buf_attachment *a;
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+ struct ti_pat_buffer *buffer = dmabuf->priv;
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+
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+ a = kzalloc(sizeof(*a), GFP_KERNEL);
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+ if (!a)
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+ return -ENOMEM;
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+
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+ a->dev = attachment->dev;
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+ a->buffer = buffer;
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+ INIT_LIST_HEAD(&a->list);
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+
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+ a->table = kzalloc(sizeof(*a->table), GFP_KERNEL);
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+ if (!a->table) {
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+ kfree(a);
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+ return -ENOMEM;
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+ }
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+
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+ if (sg_alloc_table(a->table, 1, GFP_KERNEL)) {
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+ kfree(a->table);
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+ kfree(a);
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+ return -ENOMEM;
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+ }
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+
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+ sg_set_page(a->table->sgl, pfn_to_page(PFN_DOWN(buffer->offset)), buffer->size, 0);
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+
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+ attachment->priv = a;
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+
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+ mutex_lock(&buffer->lock);
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+ /* First time attachment we attach to parent */
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+ if (list_empty(&buffer->attachments)) {
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+ buffer->attachment = dma_buf_attach(buffer->i_dma_buf, buffer->pat->dev);
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+ if (IS_ERR(buffer->attachment)) {
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+ dev_err(buffer->pat->dev, "Unable to attach to parent DMA-BUF\n");
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+ mutex_unlock(&buffer->lock);
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+ kfree(a->table);
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+ kfree(a);
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+ return PTR_ERR(buffer->attachment);
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+ }
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+ }
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+ list_add(&a->list, &buffer->attachments);
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+ mutex_unlock(&buffer->lock);
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+
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+ return 0;
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+}
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+
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+static void ti_pat_dma_buf_detach(struct dma_buf *dmabuf,
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+ struct dma_buf_attachment *attachment)
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+{
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+ struct ti_pat_dma_buf_attachment *a = attachment->priv;
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+ struct ti_pat_buffer *buffer = dmabuf->priv;
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+
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+ mutex_lock(&buffer->lock);
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+ list_del(&a->list);
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+ /* Last attachment we detach from parent */
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+ if (list_empty(&buffer->attachments)) {
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+ dma_buf_detach(buffer->i_dma_buf, buffer->attachment);
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+ buffer->attachment = NULL;
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+ }
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+ mutex_unlock(&buffer->lock);
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+
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+ kfree(a->table);
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+ kfree(a);
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+}
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+
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+static unsigned int ti_pat_table_index_from_page(size_t page)
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+{
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+ /* Every 256 pages start on a 4k boundary */
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+ unsigned int boundery = page / 256;
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+ unsigned int offset = page % 256;
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+ /* Each page occupies 8 bytes in the table */
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+ return (boundery * (4096 / 8)) + offset;
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+}
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+
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+static void ti_pat_set_page(struct ti_pat_data *pat, size_t page_id, dma_addr_t dma_address)
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+{
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+ unsigned int index = ti_pat_table_index_from_page(page_id);
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+
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+ /*
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+ * Addresses will always be at least 4K aligned, so both high and low
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+ * addresses are shifted by an additional 12 bits before being written
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+ * to the PAT.
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+ */
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+ u32 base_l = dma_address >> 12;
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+ u32 base_h = dma_address >> 44;
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+
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+ dev_dbg(pat->dev, "Enabling PAT index: %zu pointing to %pad\n", page_id, &dma_address);
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+
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+ regmap_fields_write(pat->fields[F_TABLE_ADDRL], index, base_l);
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+ regmap_fields_write(pat->fields[F_TABLE_ADDRH], index, base_h);
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+ regmap_fields_write(pat->fields[F_TABLE_ENABLE], index, 1);
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+}
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+
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+static void ti_pat_unset_page(struct ti_pat_data *pat, size_t page_id)
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+{
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+ unsigned int index = ti_pat_table_index_from_page(page_id);
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+
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+ dev_dbg(pat->dev, "Disabling PAT index: %zu\n", page_id);
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+
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+ regmap_fields_write(pat->fields[F_TABLE_ENABLE], index, 0);
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+}
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+
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+static struct sg_table *ti_pat_map_dma_buf(struct dma_buf_attachment *attachment,
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+ enum dma_data_direction direction)
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+{
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+ struct ti_pat_dma_buf_attachment *a = attachment->priv;
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+ struct ti_pat_buffer *buffer = a->buffer;
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+ struct ti_pat_data *pat = buffer->pat;
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+ struct sg_table *table = a->table;
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+ struct scatterlist *s;
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+ unsigned int i, s_len;
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+ size_t page_id;
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+ int ret;
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+
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+ mutex_lock(&buffer->lock);
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+ /* First time mapping we map to parent */
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+ if (!buffer->map_count) {
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+ buffer->sgt = dma_buf_map_attachment(buffer->attachment, DMA_BIDIRECTIONAL);
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+ if (IS_ERR(buffer->sgt)) {
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+ dev_err(pat->dev, "Unable to map parent DMA-BUF\n");
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+ return buffer->sgt;
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+ }
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+
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+ /* And program PAT area for this set of pages */
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+ page_id = (buffer->offset - pat->window_base) / pat->page_size;
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+ for_each_sg(buffer->sgt->sgl, s, buffer->sgt->nents, i) {
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+ if (s->offset) {
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+ dev_err(pat->dev, "Cannot use offset buffers\n");
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+ ret = -EINVAL;
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+ goto unmap;
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+ }
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+
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+ if (s->length % pat->page_size) {
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+ dev_err(pat->dev, "Cannot use buffers not a multiple of page size\n");
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+ ret = -EINVAL;
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+ goto unmap;
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+ }
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+
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+ for (s_len = 0; s_len < s->length; s_len += pat->page_size)
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+ ti_pat_set_page(pat, page_id++, s->dma_address + s_len);
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+ }
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+ }
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+ buffer->map_count++;
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+ mutex_unlock(&buffer->lock);
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+
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+ /* Map the attached device's table to get DMA addresses */
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+ if (!dma_map_sg_attrs(attachment->dev, table->sgl, table->nents, direction, DMA_ATTR_SKIP_CPU_SYNC))
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+ return ERR_PTR(-ENOMEM);
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+
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+ return table;
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+
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+unmap:
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+ dma_buf_unmap_attachment(buffer->attachment, buffer->sgt, DMA_BIDIRECTIONAL);
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+ mutex_unlock(&buffer->lock);
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+ return ERR_PTR(ret);
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+}
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+
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+static void ti_pat_unmap_dma_buf(struct dma_buf_attachment *attachment,
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+ struct sg_table *table,
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+ enum dma_data_direction direction)
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+{
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+ struct ti_pat_dma_buf_attachment *a = attachment->priv;
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+ struct ti_pat_buffer *buffer = a->buffer;
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+ struct ti_pat_data *pat = buffer->pat;
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+
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+ /* Unmap the attached device's table */
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+ dma_unmap_sg_attrs(attachment->dev, table->sgl, table->nents, direction, DMA_ATTR_SKIP_CPU_SYNC);
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+
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+ mutex_lock(&buffer->lock);
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+ buffer->map_count--;
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+ /* Last mapping we unmap from parent */
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+ if (!buffer->map_count) {
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+ /* Disable PAT pages for this area */
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+ size_t page_start = (buffer->offset - pat->window_base) / pat->page_size;
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+ size_t page_end = page_start + (buffer->size / pat->page_size);
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+
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+ for (; page_start < page_end; page_start++)
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+ ti_pat_unset_page(pat, page_start);
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+
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+ dma_buf_unmap_attachment(buffer->attachment, buffer->sgt, DMA_BIDIRECTIONAL);
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+ buffer->sgt = NULL;
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+ }
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+ mutex_unlock(&buffer->lock);
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+}
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+
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+static void ti_pat_dma_buf_release(struct dma_buf *dmabuf)
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+{
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+ struct ti_pat_buffer *buffer = dmabuf->priv;
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+
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+ if (buffer->attachment && buffer->sgt)
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+ dma_buf_unmap_attachment(buffer->attachment, buffer->sgt, DMA_BIDIRECTIONAL);
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+ if (buffer->i_dma_buf && !IS_ERR_OR_NULL(buffer->attachment))
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+ dma_buf_detach(buffer->i_dma_buf, buffer->attachment);
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+ if (buffer->i_dma_buf)
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+ dma_buf_put(buffer->i_dma_buf);
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+
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+ if (buffer->offset)
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+ gen_pool_free(buffer->pat->pool, buffer->offset, buffer->size);
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+
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+ kfree(buffer);
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+}
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+
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+static const struct dma_buf_ops dma_buf_ops = {
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+ .attach = ti_pat_dma_buf_attach,
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+ .detach = ti_pat_dma_buf_detach,
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+
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+ .map_dma_buf = ti_pat_map_dma_buf,
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+ .unmap_dma_buf = ti_pat_unmap_dma_buf,
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+
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+ .release = ti_pat_dma_buf_release,
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+};
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+
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+int ti_pat_export(struct ti_pat_data *pat,
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+ struct dma_buf *i_dma_buf,
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+ struct dma_buf **e_dma_buf)
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+{
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+ struct ti_pat_buffer *buffer;
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+ DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
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+ int ret;
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+
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+ buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
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+ if (!buffer)
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+ return -ENOMEM;
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+
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+ buffer->pat = pat;
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+ buffer->i_dma_buf = i_dma_buf;
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+ buffer->size = buffer->i_dma_buf->size;
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+ mutex_init(&buffer->lock);
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+ INIT_LIST_HEAD(&buffer->attachments);
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+ buffer->map_count = 0;
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+
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+ /* Reserve PAT space */
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+ buffer->offset = gen_pool_alloc(buffer->pat->pool, buffer->size);
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+ if (!buffer->offset) {
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+ ret = -ENOMEM;
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+ goto free_buffer;
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+ }
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|
|
+
|
|
|
+ exp_info.ops = &dma_buf_ops;
|
|
|
+ exp_info.size = buffer->size;
|
|
|
+ exp_info.flags = O_RDWR;
|
|
|
+ exp_info.priv = buffer;
|
|
|
+
|
|
|
+ *e_dma_buf = dma_buf_export(&exp_info);
|
|
|
+ if (IS_ERR(*e_dma_buf)) {
|
|
|
+ ret = PTR_ERR(*e_dma_buf);
|
|
|
+ goto free_pool;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+free_pool:
|
|
|
+ gen_pool_free(buffer->pat->pool, buffer->offset, buffer->size);
|
|
|
+free_buffer:
|
|
|
+ kfree(buffer);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(ti_pat_export);
|
|
|
+
|
|
|
+static long ti_pat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|
|
+{
|
|
|
+ struct ti_pat_data *pat = container_of(file->private_data, struct ti_pat_data, mdev);
|
|
|
+
|
|
|
+ switch (cmd) {
|
|
|
+ case TI_PAT_IOC_EXPORT:
|
|
|
+ {
|
|
|
+ struct ti_pat_export_data export;
|
|
|
+ struct dma_buf *i_dma_buf;
|
|
|
+ struct dma_buf *e_dma_buf;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (_IOC_SIZE(cmd) > sizeof(export))
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ if (copy_from_user(&export, (void __user *)arg, _IOC_SIZE(cmd)))
|
|
|
+ return -EFAULT;
|
|
|
+
|
|
|
+ i_dma_buf = dma_buf_get(export.fd);
|
|
|
+ if (IS_ERR(i_dma_buf))
|
|
|
+ return PTR_ERR(i_dma_buf);
|
|
|
+
|
|
|
+ ret = ti_pat_export(pat, i_dma_buf, &e_dma_buf);
|
|
|
+ if (ret) {
|
|
|
+ dma_buf_put(i_dma_buf);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ export.fd = dma_buf_fd(e_dma_buf, O_CLOEXEC);
|
|
|
+ if (export.fd < 0) {
|
|
|
+ dma_buf_put(e_dma_buf);
|
|
|
+ dma_buf_put(i_dma_buf);
|
|
|
+ return export.fd;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (copy_to_user((void __user *)arg, &export, _IOC_SIZE(cmd)))
|
|
|
+ return -EFAULT;
|
|
|
+
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ default:
|
|
|
+ return -ENOTTY;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct file_operations ti_pat_fops = {
|
|
|
+ .owner = THIS_MODULE,
|
|
|
+ .unlocked_ioctl = ti_pat_ioctl,
|
|
|
+#ifdef CONFIG_COMPAT
|
|
|
+ .compat_ioctl = ti_pat_ioctl,
|
|
|
+#endif
|
|
|
+};
|
|
|
+
|
|
|
+static const struct of_device_id ti_pat_of_match[] = {
|
|
|
+ { .compatible = "ti,j721e-pat", },
|
|
|
+ { /* sentinel */ },
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, ti_pat_of_match);
|
|
|
+
|
|
|
+static int ti_pat_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct ti_pat_data *pat;
|
|
|
+ struct resource *res;
|
|
|
+ void __iomem *base;
|
|
|
+ struct regmap *mmrs_map;
|
|
|
+ struct regmap *table_map;
|
|
|
+ unsigned int revision_major;
|
|
|
+ unsigned int revision_minor;
|
|
|
+ resource_size_t size;
|
|
|
+ size_t page_size;
|
|
|
+ int i, ret;
|
|
|
+
|
|
|
+ pat = devm_kzalloc(&pdev->dev, sizeof(*pat), GFP_KERNEL);
|
|
|
+ if (!pat)
|
|
|
+ return -ENOMEM;
|
|
|
+ platform_set_drvdata(pdev, pat);
|
|
|
+ pat->dev = &pdev->dev;
|
|
|
+
|
|
|
+ /* Set DMA mask to 64 bits */
|
|
|
+ ret = dma_set_mask_and_coherent(pat->dev, DMA_BIT_MASK(64));
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to set coherent mask to 64");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* MMRS */
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmrs");
|
|
|
+ if (!res) {
|
|
|
+ dev_err(pat->dev, "Unable to find MMRS IO resource\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+ base = devm_ioremap_resource(pat->dev, res);
|
|
|
+ if (IS_ERR(base))
|
|
|
+ return PTR_ERR(base);
|
|
|
+
|
|
|
+ mmrs_map = devm_regmap_init_mmio(pat->dev, base, &ti_pat_regmap_config);
|
|
|
+ if (IS_ERR(mmrs_map)) {
|
|
|
+ dev_err(pat->dev, "Unable to allocate MMRS register map\n");
|
|
|
+ return PTR_ERR(mmrs_map);
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < F_MMRS_FIELDS; i++) {
|
|
|
+ pat->fields[i] = devm_regmap_field_alloc(pat->dev, mmrs_map, ti_pat_reg_fields[i]);
|
|
|
+ if (IS_ERR(pat->fields[i])) {
|
|
|
+ dev_err(pat->dev, "Unable to allocate Regmap fields\n");
|
|
|
+ return PTR_ERR(pat->fields[i]);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = regmap_read(mmrs_map, TI_PAT_MMRS_CONFIG, &pat->page_count);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to read device page count\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = regmap_field_read(pat->fields[F_PID_MAJOR], &revision_major);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to read device major revision\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = regmap_field_read(pat->fields[F_PID_MINOR], &revision_minor);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to read device minor revision\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_info(pat->dev, "Found PAT Rev %d.%d with %d pages\n", revision_major, revision_minor, pat->page_count);
|
|
|
+
|
|
|
+ /* TABLE */
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "table");
|
|
|
+ if (!res) {
|
|
|
+ dev_err(pat->dev, "Unable to find TABLE IO resource\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+ base = devm_ioremap_resource(pat->dev, res);
|
|
|
+ if (IS_ERR(base))
|
|
|
+ return PTR_ERR(base);
|
|
|
+
|
|
|
+ /* 256 pages per 4KB of table space */
|
|
|
+ size = resource_size(res);
|
|
|
+ if (size != (pat->page_count << 4))
|
|
|
+ dev_warn(pat->dev, "TABLE region size (%llu) does not match reported page count\n", size);
|
|
|
+
|
|
|
+ table_map = devm_regmap_init_mmio(pat->dev, base, &ti_pat_regmap_config);
|
|
|
+ if (IS_ERR(table_map)) {
|
|
|
+ dev_err(pat->dev, "Unable to allocate TABLE register map\n");
|
|
|
+ return PTR_ERR(table_map);
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = F_MMRS_FIELDS + 1; i < F_MAX_FIELDS; i++) {
|
|
|
+ ti_pat_reg_fields[i].id_size = ti_pat_table_index_from_page(pat->page_count);
|
|
|
+ ti_pat_reg_fields[i].id_offset = 8; /* 8 bytes per entry */
|
|
|
+ pat->fields[i] = devm_regmap_field_alloc(pat->dev, table_map, ti_pat_reg_fields[i]);
|
|
|
+ if (IS_ERR(pat->fields[i])) {
|
|
|
+ dev_err(pat->dev, "Unable to allocate Regmap fields\n");
|
|
|
+ return PTR_ERR(pat->fields[i]);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* WINDOW */
|
|
|
+ ret = device_property_read_u64(pat->dev, "ti,pat-window-base", &pat->window_base);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to find ti,pat-window-base\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = device_property_read_u64(pat->dev, "ti,pat-window-size", &size);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to find ti,pat-window-size\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ pat->page_size = PAGE_SIZE;
|
|
|
+ for (page_size = 0; page_size < ARRAY_SIZE(ti_pat_page_sizes); page_size++)
|
|
|
+ if (ti_pat_page_sizes[page_size] == pat->page_size)
|
|
|
+ break;
|
|
|
+ if (page_size == ARRAY_SIZE(ti_pat_page_sizes)) {
|
|
|
+ dev_err(pat->dev, "Unsupported PAGE_SIZE (%d)\n", pat->page_size);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ regmap_field_write(pat->fields[F_CONTROL_PAGE_SIZE], page_size);
|
|
|
+
|
|
|
+ /* Enable this PAT module */
|
|
|
+ regmap_field_write(pat->fields[F_CONTROL_EN], 1);
|
|
|
+
|
|
|
+ pat->pool = gen_pool_create(PAGE_SHIFT, -1);
|
|
|
+ if (!pat->pool)
|
|
|
+ return -ENOMEM;
|
|
|
+ gen_pool_add(pat->pool, pat->window_base, size, -1);
|
|
|
+
|
|
|
+ pat->mdev.minor = MISC_DYNAMIC_MINOR;
|
|
|
+ pat->mdev.name = pdev->name;
|
|
|
+ pat->mdev.fops = &ti_pat_fops;
|
|
|
+ pat->mdev.parent = NULL;
|
|
|
+ ret = misc_register(&pat->mdev);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pat->dev, "Unable to register misc device\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct platform_driver ti_pat_driver = {
|
|
|
+ .probe = ti_pat_probe,
|
|
|
+ .driver = {
|
|
|
+ .name = "ti-pat",
|
|
|
+ .of_match_table = ti_pat_of_match,
|
|
|
+ },
|
|
|
+};
|
|
|
+module_platform_driver(ti_pat_driver);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
|
|
|
+MODULE_DESCRIPTION("TI PAT mapped DMA-BUF memory exporter");
|
|
|
+MODULE_LICENSE("GPL v2");
|
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