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@@ -25,7 +25,6 @@
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#define MII_BCM7XXX_100TX_DISC 0x14
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#define MII_BCM7XXX_100TX_DISC 0x14
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#define MII_BCM7XXX_AUX_MODE 0x1d
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#define MII_BCM7XXX_AUX_MODE 0x1d
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#define MII_BCM7XX_64CLK_MDIO BIT(12)
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#define MII_BCM7XX_64CLK_MDIO BIT(12)
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-#define MII_BCM7XXX_CORE_BASE1E 0x1e
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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@@ -46,8 +45,6 @@
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#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
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#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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-#define CORE_EXPB0 0xb0
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-
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static void r_rc_cal_reset(struct phy_device *phydev)
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static void r_rc_cal_reset(struct phy_device *phydev)
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{
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{
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/* Reset R_CAL/RC_CAL Engine */
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/* Reset R_CAL/RC_CAL Engine */
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@@ -76,7 +73,7 @@ static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
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/* Switch to CORE_BASE1E */
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/* Switch to CORE_BASE1E */
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- phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
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+ phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
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r_rc_cal_reset(phydev);
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r_rc_cal_reset(phydev);
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@@ -127,7 +124,7 @@ static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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- phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);
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+ phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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@@ -155,7 +152,7 @@ static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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- phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);
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+ phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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