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@@ -86,7 +86,7 @@ struct fotg210_hcd { /* one per controller */
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/* glue to PCI and HCD framework */
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struct fotg210_caps __iomem *caps;
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struct fotg210_regs __iomem *regs;
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- struct fotg210_dbg_port __iomem *debug;
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+ struct ehci_dbg_port __iomem *debug;
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__u32 hcs_params; /* cached register copy */
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spinlock_t lock;
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@@ -295,17 +295,6 @@ struct fotg210_regs {
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#define GMIR_MDEV_INT (1 << 0)
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};
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-/* Appendix C, Debug port ... intended for use with special "debug devices"
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- * that can help if there's no serial console. (nonstandard enumeration.)
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- */
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-struct fotg210_dbg_port {
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- u32 control;
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- u32 pids;
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- u32 data03;
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- u32 data47;
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- u32 address;
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-};
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-
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/*-------------------------------------------------------------------------*/
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#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
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