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@@ -23,6 +23,7 @@
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "gmc_v9_0.h"
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+#include "amdgpu_atomfirmware.h"
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#include "vega10/soc15ip.h"
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#include "vega10/HDP/hdp_4_0_offset.h"
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@@ -442,43 +443,46 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
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u32 tmp;
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int chansize, numchan;
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- /* hbm memory channel size */
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- chansize = 128;
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-
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- tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
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- tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
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- tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
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- switch (tmp) {
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- case 0:
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- default:
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- numchan = 1;
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- break;
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- case 1:
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- numchan = 2;
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- break;
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- case 2:
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- numchan = 0;
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- break;
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- case 3:
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- numchan = 4;
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- break;
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- case 4:
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- numchan = 0;
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- break;
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- case 5:
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- numchan = 8;
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- break;
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- case 6:
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- numchan = 0;
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- break;
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- case 7:
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- numchan = 16;
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- break;
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- case 8:
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- numchan = 2;
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- break;
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+ adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
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+ if (!adev->mc.vram_width) {
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+ /* hbm memory channel size */
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+ chansize = 128;
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+
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+ tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
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+ tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
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+ tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
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+ switch (tmp) {
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+ case 0:
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+ default:
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+ numchan = 1;
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+ break;
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+ case 1:
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+ numchan = 2;
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+ break;
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+ case 2:
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+ numchan = 0;
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+ break;
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+ case 3:
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+ numchan = 4;
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+ break;
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+ case 4:
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+ numchan = 0;
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+ break;
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+ case 5:
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+ numchan = 8;
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+ break;
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+ case 6:
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+ numchan = 0;
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+ break;
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+ case 7:
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+ numchan = 16;
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+ break;
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+ case 8:
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+ numchan = 2;
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+ break;
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+ }
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+ adev->mc.vram_width = numchan * chansize;
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}
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- adev->mc.vram_width = numchan * chansize;
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/* Could aper size report 0 ? */
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adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
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