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@@ -117,11 +117,7 @@ static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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- ret = pcie_phy_poll_ack(dbi_base, 0);
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- if (ret)
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- return ret;
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-
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- return 0;
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+ return pcie_phy_poll_ack(dbi_base, 0);
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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@@ -148,11 +144,7 @@ static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
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/* deassert Read signal */
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writel(0x00, dbi_base + PCIE_PHY_CTRL);
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- ret = pcie_phy_poll_ack(dbi_base, 0);
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- if (ret)
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- return ret;
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-
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- return 0;
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+ return pcie_phy_poll_ack(dbi_base, 0);
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}
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static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
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