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@@ -551,8 +551,7 @@ static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
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if (IS_CHAN_HT40(chan)) {
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phymode |= AR_PHY_GC_DYN2040_EN;
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/* Configure control (primary) channel at +-10MHz */
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- if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
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- (chan->chanmode == CHANNEL_G_HT40PLUS))
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+ if (IS_CHAN_HT40PLUS(chan))
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phymode |= AR_PHY_GC_DYN2040_PRI_CH;
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}
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@@ -682,41 +681,22 @@ static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
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{
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int ret;
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- switch (chan->chanmode) {
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- case CHANNEL_A:
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- case CHANNEL_A_HT20:
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- if (chan->channel <= 5350)
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- ret = 1;
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- else if ((chan->channel > 5350) && (chan->channel <= 5600))
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- ret = 3;
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+ if (IS_CHAN_2GHZ(chan)) {
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+ if (IS_CHAN_HT40(chan))
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+ return 7;
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else
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- ret = 5;
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- break;
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-
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- case CHANNEL_A_HT40PLUS:
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- case CHANNEL_A_HT40MINUS:
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- if (chan->channel <= 5350)
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- ret = 2;
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- else if ((chan->channel > 5350) && (chan->channel <= 5600))
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- ret = 4;
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- else
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- ret = 6;
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- break;
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-
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- case CHANNEL_G:
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- case CHANNEL_G_HT20:
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- case CHANNEL_B:
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- ret = 8;
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- break;
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+ return 8;
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+ }
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- case CHANNEL_G_HT40PLUS:
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- case CHANNEL_G_HT40MINUS:
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- ret = 7;
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- break;
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+ if (chan->channel <= 5350)
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+ ret = 1;
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+ else if ((chan->channel > 5350) && (chan->channel <= 5600))
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+ ret = 3;
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+ else
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+ ret = 5;
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- default:
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- ret = -EINVAL;
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- }
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+ if (IS_CHAN_HT40(chan))
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+ ret++;
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return ret;
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}
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@@ -727,28 +707,10 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
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unsigned int regWrites = 0, i;
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u32 modesIndex;
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- switch (chan->chanmode) {
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- case CHANNEL_A:
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- case CHANNEL_A_HT20:
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- modesIndex = 1;
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- break;
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- case CHANNEL_A_HT40PLUS:
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- case CHANNEL_A_HT40MINUS:
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- modesIndex = 2;
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- break;
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- case CHANNEL_G:
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- case CHANNEL_G_HT20:
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- case CHANNEL_B:
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- modesIndex = 4;
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- break;
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- case CHANNEL_G_HT40PLUS:
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- case CHANNEL_G_HT40MINUS:
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- modesIndex = 3;
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- break;
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-
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- default:
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- return -EINVAL;
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- }
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+ if (IS_CHAN_5GHZ(chan))
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+ modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
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+ else
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+ modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
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/*
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* SOC, MAC, BB, RADIO initvals.
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@@ -1273,12 +1235,11 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
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aniState = &ah->ani;
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iniDef = &aniState->iniDef;
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- ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
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+ ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
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ah->hw_version.macVersion,
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ah->hw_version.macRev,
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ah->opmode,
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- chan->channel,
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- chan->channelFlags);
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+ chan->channel);
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val = REG_READ(ah, AR_PHY_SFCORR);
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iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
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@@ -1536,28 +1497,10 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
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unsigned int regWrites = 0;
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u32 modesIndex;
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- switch (chan->chanmode) {
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- case CHANNEL_A:
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- case CHANNEL_A_HT20:
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- modesIndex = 1;
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- break;
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- case CHANNEL_A_HT40PLUS:
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- case CHANNEL_A_HT40MINUS:
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- modesIndex = 2;
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- break;
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- case CHANNEL_G:
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- case CHANNEL_G_HT20:
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- case CHANNEL_B:
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- modesIndex = 4;
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- break;
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- case CHANNEL_G_HT40PLUS:
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- case CHANNEL_G_HT40MINUS:
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- modesIndex = 3;
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- break;
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-
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- default:
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- return -EINVAL;
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- }
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+ if (IS_CHAN_5GHZ(chan))
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+ modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
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+ else
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+ modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
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if (modesIndex == ah->modes_index) {
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*ini_reloaded = false;
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