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@@ -214,7 +214,15 @@ define_machine(corenet_generic) {
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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+/*
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+ * Core reset may cause issue if using the proxy mode of MPIC.
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+ * So, use the mixed mode of MPIC if enabling CPU hotplug.
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+ */
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .get_irq = mpic_get_irq,
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+#else
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.get_irq = mpic_get_coreint_irq,
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+#endif
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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