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@@ -47,7 +47,13 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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-/include/ "skeleton.dtsi"
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+#include "skeleton.dtsi"
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/thermal/thermal.h>
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+
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+#include <dt-bindings/dma/sun4i-a10.h>
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+#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -76,16 +82,49 @@
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<&ahb_gates 44>;
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status = "disabled";
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};
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+
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+ framebuffer@1 {
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+ compatible = "allwinner,simple-framebuffer",
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+ "simple-framebuffer";
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+ allwinner,pipeline = "de_be0-lcd0";
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+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
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+ status = "disabled";
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+ };
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+
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+ framebuffer@2 {
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+ compatible = "allwinner,simple-framebuffer",
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+ "simple-framebuffer";
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+ allwinner,pipeline = "de_be0-lcd0-tve0";
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+ clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
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+ <&ahb_gates 44>;
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+ status = "disabled";
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+ };
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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+ clocks = <&cpu>;
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+ clock-latency = <244144>; /* 8 32k periods */
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+ operating-points = <
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+ /* kHz uV */
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+ 1008000 1450000
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+ 960000 1400000
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+ 912000 1400000
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+ 864000 1300000
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+ 720000 1200000
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+ 528000 1100000
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+ 312000 1000000
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+ 144000 900000
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+ >;
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+ #cooling-cells = <2>;
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+ cooling-min-level = <0>;
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+ cooling-max-level = <7>;
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};
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cpu@1 {
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@@ -95,22 +134,54 @@
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};
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};
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+ thermal-zones {
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+ cpu_thermal {
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+ /* milliseconds */
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&rtp>;
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu_alert0>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+
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+ trips {
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+ cpu_alert0: cpu_alert0 {
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+ /* milliCelsius */
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+ temperature = <75000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cpu_crit: cpu_crit {
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+ /* milliCelsius */
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+ temperature = <100000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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+
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memory {
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reg = <0x40000000 0x80000000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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- interrupts = <1 13 0xf08>,
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- <1 14 0xf08>,
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- <1 11 0xf08>,
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- <1 10 0xf08>;
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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- interrupts = <0 120 4>,
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- <0 121 4>;
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+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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@@ -462,13 +533,13 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01c00030 0x0c>;
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- interrupts = <0 0 4>;
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+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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- interrupts = <0 27 4>;
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+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 6>;
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#dma-cells = <2>;
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};
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@@ -476,10 +547,11 @@
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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- interrupts = <0 10 4>;
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+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 20>, <&spi0_clk>;
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clock-names = "ahb", "mod";
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- dmas = <&dma 1 27>, <&dma 1 26>;
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+ dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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+ <&dma SUN4I_DMA_DEDICATED 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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@@ -489,10 +561,11 @@
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spi1: spi@01c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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- interrupts = <0 11 4>;
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+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 21>, <&spi1_clk>;
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clock-names = "ahb", "mod";
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- dmas = <&dma 1 9>, <&dma 1 8>;
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+ dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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+ <&dma SUN4I_DMA_DEDICATED 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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@@ -502,12 +575,12 @@
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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- interrupts = <0 55 4>;
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+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 17>;
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status = "disabled";
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};
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- mdio@01c0b080 {
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+ mdio: mdio@01c0b080 {
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compatible = "allwinner,sun4i-a10-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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@@ -520,7 +593,7 @@
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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- interrupts = <0 32 4>;
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+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -529,7 +602,7 @@
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb_gates 9>, <&mmc1_clk>;
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clock-names = "ahb", "mmc";
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- interrupts = <0 33 4>;
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+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -538,7 +611,7 @@
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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- interrupts = <0 34 4>;
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+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -547,7 +620,7 @@
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reg = <0x01c12000 0x1000>;
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clocks = <&ahb_gates 11>, <&mmc3_clk>;
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clock-names = "ahb", "mmc";
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- interrupts = <0 35 4>;
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+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@@ -566,7 +639,7 @@
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ehci0: usb@01c14000 {
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compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
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reg = <0x01c14000 0x100>;
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- interrupts = <0 39 4>;
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+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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@@ -576,7 +649,7 @@
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ohci0: usb@01c14400 {
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compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
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reg = <0x01c14400 0x100>;
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- interrupts = <0 64 4>;
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+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clk 6>, <&ahb_gates 2>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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@@ -586,10 +659,11 @@
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spi2: spi@01c17000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c17000 0x1000>;
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- interrupts = <0 12 4>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 22>, <&spi2_clk>;
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clock-names = "ahb", "mod";
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- dmas = <&dma 1 29>, <&dma 1 28>;
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+ dmas = <&dma SUN4I_DMA_DEDICATED 29>,
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+ <&dma SUN4I_DMA_DEDICATED 28>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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@@ -599,7 +673,7 @@
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ahci: sata@01c18000 {
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compatible = "allwinner,sun4i-a10-ahci";
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reg = <0x01c18000 0x1000>;
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- interrupts = <0 56 4>;
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+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll6 0>, <&ahb_gates 25>;
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status = "disabled";
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};
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@@ -607,7 +681,7 @@
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ehci1: usb@01c1c000 {
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compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
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reg = <0x01c1c000 0x100>;
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- interrupts = <0 40 4>;
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+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 3>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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@@ -617,7 +691,7 @@
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ohci1: usb@01c1c400 {
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compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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- interrupts = <0 65 4>;
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+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clk 7>, <&ahb_gates 4>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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@@ -627,10 +701,11 @@
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spi3: spi@01c1f000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c1f000 0x1000>;
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- interrupts = <0 50 4>;
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+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 23>, <&spi3_clk>;
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clock-names = "ahb", "mod";
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- dmas = <&dma 1 31>, <&dma 1 30>;
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+ dmas = <&dma SUN4I_DMA_DEDICATED 31>,
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+ <&dma SUN4I_DMA_DEDICATED 30>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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@@ -640,7 +715,7 @@
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun7i-a20-pinctrl";
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reg = <0x01c20800 0x400>;
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- interrupts = <0 28 4>;
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+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 5>;
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gpio-controller;
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interrupt-controller;
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@@ -651,99 +726,99 @@
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pwm0_pins_a: pwm0@0 {
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allwinner,pins = "PB2";
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allwinner,function = "pwm";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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pwm1_pins_a: pwm1@0 {
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allwinner,pins = "PI3";
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allwinner,function = "pwm";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PB22", "PB23";
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allwinner,function = "uart0";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart2_pins_a: uart2@0 {
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allwinner,pins = "PI16", "PI17", "PI18", "PI19";
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allwinner,function = "uart2";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_pins_a: uart3@0 {
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allwinner,pins = "PG6", "PG7", "PG8", "PG9";
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allwinner,function = "uart3";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_pins_b: uart3@1 {
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allwinner,pins = "PH0", "PH1";
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allwinner,function = "uart3";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart4_pins_a: uart4@0 {
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allwinner,pins = "PG10", "PG11";
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allwinner,function = "uart4";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart5_pins_a: uart5@0 {
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allwinner,pins = "PI10", "PI11";
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allwinner,function = "uart5";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart6_pins_a: uart6@0 {
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allwinner,pins = "PI12", "PI13";
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allwinner,function = "uart6";
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- allwinner,drive = <0>;
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- allwinner,pull = <0>;
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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|
uart7_pins_a: uart7@0 {
|
|
|
allwinner,pins = "PI20", "PI21";
|
|
|
allwinner,function = "uart7";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
|
allwinner,pins = "PB0", "PB1";
|
|
|
allwinner,function = "i2c0";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
|
allwinner,pins = "PB18", "PB19";
|
|
|
allwinner,function = "i2c1";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
|
allwinner,pins = "PB20", "PB21";
|
|
|
allwinner,function = "i2c2";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
i2c3_pins_a: i2c3@0 {
|
|
|
allwinner,pins = "PI0", "PI1";
|
|
|
allwinner,function = "i2c3";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
emac_pins_a: emac0@0 {
|
|
|
@@ -753,22 +828,22 @@
|
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
|
"PA15", "PA16";
|
|
|
allwinner,function = "emac";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
clk_out_a_pins_a: clk_out_a@0 {
|
|
|
allwinner,pins = "PI12";
|
|
|
allwinner,function = "clk_out_a";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
clk_out_b_pins_a: clk_out_b@0 {
|
|
|
allwinner,pins = "PI13";
|
|
|
allwinner,function = "clk_out_b";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
gmac_pins_mii_a: gmac_mii@0 {
|
|
|
@@ -778,8 +853,8 @@
|
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
|
"PA15", "PA16";
|
|
|
allwinner,function = "gmac";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
|
@@ -793,90 +868,104 @@
|
|
|
* data lines in RGMII mode use DDR mode
|
|
|
* and need a higher signal drive strength
|
|
|
*/
|
|
|
- allwinner,drive = <3>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
spi0_pins_a: spi0@0 {
|
|
|
allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
|
|
|
allwinner,function = "spi0";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
spi1_pins_a: spi1@0 {
|
|
|
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
|
|
|
allwinner,function = "spi1";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
spi2_pins_a: spi2@0 {
|
|
|
allwinner,pins = "PC19", "PC20", "PC21", "PC22";
|
|
|
allwinner,function = "spi2";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
spi2_pins_b: spi2@1 {
|
|
|
allwinner,pins = "PB14", "PB15", "PB16", "PB17";
|
|
|
allwinner,function = "spi2";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
|
allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
|
|
|
allwinner,function = "mmc0";
|
|
|
- allwinner,drive = <2>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
|
|
|
allwinner,pins = "PH1";
|
|
|
allwinner,function = "gpio_in";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <1>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
};
|
|
|
|
|
|
mmc2_pins_a: mmc2@0 {
|
|
|
allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
|
|
|
allwinner,function = "mmc2";
|
|
|
- allwinner,drive = <2>;
|
|
|
- allwinner,pull = <1>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
};
|
|
|
|
|
|
mmc3_pins_a: mmc3@0 {
|
|
|
allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
|
|
|
allwinner,function = "mmc3";
|
|
|
- allwinner,drive = <2>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
ir0_pins_a: ir0@0 {
|
|
|
allwinner,pins = "PB3","PB4";
|
|
|
allwinner,function = "ir0";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
ir1_pins_a: ir1@0 {
|
|
|
allwinner,pins = "PB22","PB23";
|
|
|
allwinner,function = "ir1";
|
|
|
- allwinner,drive = <0>;
|
|
|
- allwinner,pull = <0>;
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ps20_pins_a: ps20@0 {
|
|
|
+ allwinner,pins = "PI20", "PI21";
|
|
|
+ allwinner,function = "ps2";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ps21_pins_a: ps21@0 {
|
|
|
+ allwinner,pins = "PH12", "PH13";
|
|
|
+ allwinner,function = "ps2";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
timer@01c20c00 {
|
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
|
reg = <0x01c20c00 0x90>;
|
|
|
- interrupts = <0 22 4>,
|
|
|
- <0 23 4>,
|
|
|
- <0 24 4>,
|
|
|
- <0 25 4>,
|
|
|
- <0 67 4>,
|
|
|
- <0 68 4>;
|
|
|
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&osc24M>;
|
|
|
};
|
|
|
|
|
|
@@ -888,7 +977,7 @@
|
|
|
rtc: rtc@01c20d00 {
|
|
|
compatible = "allwinner,sun7i-a20-rtc";
|
|
|
reg = <0x01c20d00 0x20>;
|
|
|
- interrupts = <0 24 4>;
|
|
|
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
};
|
|
|
|
|
|
pwm: pwm@01c20e00 {
|
|
|
@@ -903,7 +992,7 @@
|
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
|
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
|
|
clock-names = "apb", "ir";
|
|
|
- interrupts = <0 5 4>;
|
|
|
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg = <0x01c21800 0x40>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
@@ -912,11 +1001,18 @@
|
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
|
clocks = <&apb0_gates 7>, <&ir1_clk>;
|
|
|
clock-names = "apb", "ir";
|
|
|
- interrupts = <0 6 4>;
|
|
|
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg = <0x01c21c00 0x40>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ lradc: lradc@01c22800 {
|
|
|
+ compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
|
+ reg = <0x01c22800 0x100>;
|
|
|
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
sid: eeprom@01c23800 {
|
|
|
compatible = "allwinner,sun7i-a20-sid";
|
|
|
reg = <0x01c23800 0x200>;
|
|
|
@@ -925,13 +1021,14 @@
|
|
|
rtp: rtp@01c25000 {
|
|
|
compatible = "allwinner,sun4i-a10-ts";
|
|
|
reg = <0x01c25000 0x100>;
|
|
|
- interrupts = <0 29 4>;
|
|
|
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #thermal-sensor-cells = <0>;
|
|
|
};
|
|
|
|
|
|
uart0: serial@01c28000 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c28000 0x400>;
|
|
|
- interrupts = <0 1 4>;
|
|
|
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 16>;
|
|
|
@@ -941,7 +1038,7 @@
|
|
|
uart1: serial@01c28400 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c28400 0x400>;
|
|
|
- interrupts = <0 2 4>;
|
|
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 17>;
|
|
|
@@ -951,7 +1048,7 @@
|
|
|
uart2: serial@01c28800 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c28800 0x400>;
|
|
|
- interrupts = <0 3 4>;
|
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 18>;
|
|
|
@@ -961,7 +1058,7 @@
|
|
|
uart3: serial@01c28c00 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c28c00 0x400>;
|
|
|
- interrupts = <0 4 4>;
|
|
|
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 19>;
|
|
|
@@ -971,7 +1068,7 @@
|
|
|
uart4: serial@01c29000 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c29000 0x400>;
|
|
|
- interrupts = <0 17 4>;
|
|
|
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 20>;
|
|
|
@@ -981,7 +1078,7 @@
|
|
|
uart5: serial@01c29400 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c29400 0x400>;
|
|
|
- interrupts = <0 18 4>;
|
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 21>;
|
|
|
@@ -991,7 +1088,7 @@
|
|
|
uart6: serial@01c29800 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c29800 0x400>;
|
|
|
- interrupts = <0 19 4>;
|
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 22>;
|
|
|
@@ -1001,7 +1098,7 @@
|
|
|
uart7: serial@01c29c00 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c29c00 0x400>;
|
|
|
- interrupts = <0 20 4>;
|
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
clocks = <&apb1_gates 23>;
|
|
|
@@ -1011,7 +1108,7 @@
|
|
|
i2c0: i2c@01c2ac00 {
|
|
|
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
- interrupts = <0 7 4>;
|
|
|
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&apb1_gates 0>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
@@ -1021,7 +1118,7 @@
|
|
|
i2c1: i2c@01c2b000 {
|
|
|
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
- interrupts = <0 8 4>;
|
|
|
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&apb1_gates 1>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
@@ -1031,7 +1128,7 @@
|
|
|
i2c2: i2c@01c2b400 {
|
|
|
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
- interrupts = <0 9 4>;
|
|
|
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&apb1_gates 2>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
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@@ -1041,7 +1138,7 @@
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i2c3: i2c@01c2b800 {
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compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
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reg = <0x01c2b800 0x400>;
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- interrupts = <0 88 4>;
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+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 3>;
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status = "disabled";
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#address-cells = <1>;
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@@ -1051,7 +1148,7 @@
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i2c4: i2c@01c2c000 {
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compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
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reg = <0x01c2c000 0x400>;
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- interrupts = <0 89 4>;
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+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 15>;
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status = "disabled";
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#address-cells = <1>;
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@@ -1061,7 +1158,7 @@
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gmac: ethernet@01c50000 {
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compatible = "allwinner,sun7i-a20-gmac";
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reg = <0x01c50000 0x10000>;
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- interrupts = <0 85 4>;
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+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
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clock-names = "stmmaceth", "allwinner_gmac_tx";
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@@ -1076,10 +1173,10 @@
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hstimer@01c60000 {
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compatible = "allwinner,sun7i-a20-hstimer";
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reg = <0x01c60000 0x1000>;
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- interrupts = <0 81 4>,
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- <0 82 4>,
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- <0 83 4>,
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- <0 84 4>;
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+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb_gates 28>;
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};
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@@ -1091,7 +1188,23 @@
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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- interrupts = <1 9 0xf04>;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ };
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+
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+ ps20: ps2@01c2a000 {
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+ compatible = "allwinner,sun4i-a10-ps2";
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+ reg = <0x01c2a000 0x400>;
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+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&apb1_gates 6>;
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+ status = "disabled";
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+ };
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+
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+ ps21: ps2@01c2a400 {
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+ compatible = "allwinner,sun4i-a10-ps2";
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+ reg = <0x01c2a400 0x400>;
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+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&apb1_gates 7>;
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+ status = "disabled";
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};
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};
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};
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