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@@ -583,6 +583,26 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
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return 1;
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}
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+static void set_command_address(struct pxa3xx_nand_info *info,
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+ unsigned int page_size, uint16_t column, int page_addr)
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+{
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+ /* small page addr setting */
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+ if (page_size < PAGE_CHUNK_SIZE) {
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+ info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
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+ | (column & 0xFF);
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+
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+ info->ndcb2 = 0;
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+ } else {
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+ info->ndcb1 = ((page_addr & 0xFFFF) << 16)
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+ | (column & 0xFFFF);
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+
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+ if (page_addr & 0xFF0000)
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+ info->ndcb2 = (page_addr & 0xFF0000) >> 16;
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+ else
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+ info->ndcb2 = 0;
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+ }
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+}
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+
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static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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uint16_t column, int page_addr)
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{
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@@ -646,22 +666,8 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
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case NAND_CMD_SEQIN:
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- /* small page addr setting */
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- if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) {
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- info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
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- | (column & 0xFF);
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-
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- info->ndcb2 = 0;
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- } else {
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- info->ndcb1 = ((page_addr & 0xFFFF) << 16)
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- | (column & 0xFFFF);
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-
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- if (page_addr & 0xFF0000)
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- info->ndcb2 = (page_addr & 0xFF0000) >> 16;
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- else
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- info->ndcb2 = 0;
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- }
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+ set_command_address(info, mtd->writesize, column, page_addr);
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info->buf_count = mtd->writesize + mtd->oobsize;
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memset(info->data_buff, 0xFF, info->buf_count);
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