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@@ -53,7 +53,7 @@ static bool of_init = false;
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/*
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* Common code for all cache controllers.
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*/
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-static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
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+static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
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{
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/* wait for cache operation by line or way to complete */
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while (readl_relaxed(reg) & mask)
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@@ -73,7 +73,7 @@ static inline void l2c_set_debug(void __iomem *base, unsigned long val)
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static void __l2c_op_way(void __iomem *reg)
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{
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writel_relaxed(l2x0_way_mask, reg);
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- cache_wait_way(reg, l2x0_way_mask);
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+ l2c_wait_mask(reg, l2x0_way_mask);
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}
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static inline void l2c_unlock(void __iomem *base, unsigned num)
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@@ -94,7 +94,7 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask)
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/* cache operations by line are atomic on PL310 */
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}
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#else
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-#define cache_wait cache_wait_way
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+#define cache_wait l2c_wait_mask
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#endif
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static inline void cache_sync(void)
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