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@@ -68,6 +68,8 @@
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#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
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+#define SDHCI_MSM_MIN_CLOCK 400000
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+
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#define CDR_SELEXT_SHIFT 20
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#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
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#define CMUX_SHIFT_PHASE_SHIFT 24
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@@ -556,6 +558,19 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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+static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
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+{
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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+
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+ return clk_round_rate(msm_host->clk, ULONG_MAX);
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+}
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+
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+static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
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+{
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+ return SDHCI_MSM_MIN_CLOCK;
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+}
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+
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static const struct of_device_id sdhci_msm_dt_match[] = {
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{ .compatible = "qcom,sdhci-msm-v4" },
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{},
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@@ -567,6 +582,8 @@ static const struct sdhci_ops sdhci_msm_ops = {
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.platform_execute_tuning = sdhci_msm_execute_tuning,
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.reset = sdhci_reset,
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.set_clock = sdhci_set_clock,
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+ .get_min_clock = sdhci_msm_get_min_clock,
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+ .get_max_clock = sdhci_msm_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
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.voltage_switch = sdhci_msm_voltage_switch,
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