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@@ -44,6 +44,11 @@
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/* Fields containing pulse width data */
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#define MTK_WIDTH_MASK (GENMASK(7, 0))
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+/* IR threshold */
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+#define MTK_IRTHD 0x14
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+#define MTK_DG_CNT_MASK (GENMASK(12, 8))
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+#define MTK_DG_CNT(x) ((x) << 8)
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+
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/* Bit to enable interrupt */
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#define MTK_IRINT_EN BIT(0)
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@@ -409,6 +414,9 @@ static int mtk_ir_probe(struct platform_device *pdev)
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mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
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ir->data->fields[MTK_HW_PERIOD].reg);
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+ /* Set de-glitch counter */
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+ mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
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+
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/* Enable IR and PWM */
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val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
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val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
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