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@@ -49,7 +49,7 @@
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#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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#define SOCFPGA_NAND_CLK "nand_clk"
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#define SOCFPGA_NAND_CLK "nand_clk"
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#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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-#define SOCFPGA_MMC_CLK "mmc_clk"
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+#define SOCFPGA_MMC_CLK "sdmmc_clk"
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#define SOCFPGA_DB_CLK "gpio_db_clk"
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#define SOCFPGA_DB_CLK "gpio_db_clk"
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#define div_mask(width) ((1 << (width)) - 1)
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#define div_mask(width) ((1 << (width)) - 1)
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