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@@ -221,8 +221,10 @@ enum meson_sar_adc_chan7_mux_sel {
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struct meson_sar_adc_data {
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bool has_bl30_integration;
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+ u32 bandgap_reg;
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unsigned int resolution;
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const char *name;
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+ const struct regmap_config *regmap_config;
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};
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struct meson_sar_adc_priv {
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@@ -242,13 +244,20 @@ struct meson_sar_adc_priv {
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int calibscale;
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};
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-static const struct regmap_config meson_sar_adc_regmap_config = {
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+static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
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.reg_bits = 8,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = MESON_SAR_ADC_REG13,
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};
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+static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
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+ .reg_bits = 8,
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+ .val_bits = 32,
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+ .reg_stride = 4,
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+ .max_register = MESON_SAR_ADC_DELTA_10,
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+};
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+
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static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
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{
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struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
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@@ -600,7 +609,7 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
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init.num_parents = 1;
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priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
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- priv->clk_gate.bit_idx = fls(MESON_SAR_ADC_REG3_CLK_EN);
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+ priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
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priv->clk_gate.hw.init = &init;
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priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
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@@ -685,6 +694,20 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
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return 0;
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}
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+static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
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+{
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+ struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
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+ u32 enable_mask;
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+
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+ if (priv->data->bandgap_reg == MESON_SAR_ADC_REG11)
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+ enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
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+ else
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+ enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
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+
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+ regmap_update_bits(priv->regmap, priv->data->bandgap_reg, enable_mask,
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+ on_off ? enable_mask : 0);
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+}
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+
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static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
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{
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struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
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@@ -717,9 +740,9 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
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regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
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MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
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- regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
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- MESON_SAR_ADC_REG11_BANDGAP_EN,
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- MESON_SAR_ADC_REG11_BANDGAP_EN);
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+
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+ meson_sar_adc_set_bandgap(indio_dev, true);
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+
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
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MESON_SAR_ADC_REG3_ADC_EN,
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MESON_SAR_ADC_REG3_ADC_EN);
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@@ -739,8 +762,7 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
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err_adc_clk:
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
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MESON_SAR_ADC_REG3_ADC_EN, 0);
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- regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
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- MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
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+ meson_sar_adc_set_bandgap(indio_dev, false);
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clk_disable_unprepare(priv->sana_clk);
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err_sana_clk:
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clk_disable_unprepare(priv->core_clk);
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@@ -765,8 +787,8 @@ static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
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MESON_SAR_ADC_REG3_ADC_EN, 0);
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- regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
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- MESON_SAR_ADC_REG11_BANDGAP_EN, 0);
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+
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+ meson_sar_adc_set_bandgap(indio_dev, false);
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clk_disable_unprepare(priv->sana_clk);
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clk_disable_unprepare(priv->core_clk);
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@@ -844,30 +866,40 @@ static const struct iio_info meson_sar_adc_iio_info = {
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static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
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.has_bl30_integration = false,
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+ .bandgap_reg = MESON_SAR_ADC_DELTA_10,
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+ .regmap_config = &meson_sar_adc_regmap_config_meson8,
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.resolution = 10,
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.name = "meson-meson8-saradc",
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};
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static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
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.has_bl30_integration = false,
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+ .bandgap_reg = MESON_SAR_ADC_DELTA_10,
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+ .regmap_config = &meson_sar_adc_regmap_config_meson8,
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.resolution = 10,
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.name = "meson-meson8b-saradc",
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};
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static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
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.has_bl30_integration = true,
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+ .bandgap_reg = MESON_SAR_ADC_REG11,
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+ .regmap_config = &meson_sar_adc_regmap_config_gxbb,
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.resolution = 10,
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.name = "meson-gxbb-saradc",
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};
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static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
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.has_bl30_integration = true,
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+ .bandgap_reg = MESON_SAR_ADC_REG11,
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+ .regmap_config = &meson_sar_adc_regmap_config_gxbb,
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.resolution = 12,
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.name = "meson-gxl-saradc",
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};
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static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
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.has_bl30_integration = true,
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+ .bandgap_reg = MESON_SAR_ADC_REG11,
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+ .regmap_config = &meson_sar_adc_regmap_config_gxbb,
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.resolution = 12,
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.name = "meson-gxm-saradc",
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};
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@@ -945,7 +977,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
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return ret;
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priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
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- &meson_sar_adc_regmap_config);
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+ priv->data->regmap_config);
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if (IS_ERR(priv->regmap))
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return PTR_ERR(priv->regmap);
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