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@@ -273,16 +273,26 @@ out:
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static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
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{
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switch (hw->device_id) {
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+ case IXGBE_DEV_ID_X550EM_A_SFP:
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+ if (hw->bus.lan_id)
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+ hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
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+ else
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+ hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
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+ return ixgbe_identify_module_generic(hw);
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case IXGBE_DEV_ID_X550EM_X_SFP:
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/* set up for CS4227 usage */
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hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
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ixgbe_setup_mux_ctl(hw);
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ixgbe_check_cs4227(hw);
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+ /* Fallthrough */
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+ case IXGBE_DEV_ID_X550EM_A_SFP_N:
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return ixgbe_identify_module_generic(hw);
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case IXGBE_DEV_ID_X550EM_X_KX4:
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hw->phy.type = ixgbe_phy_x550em_kx4;
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break;
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case IXGBE_DEV_ID_X550EM_X_KR:
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+ case IXGBE_DEV_ID_X550EM_A_KR:
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+ case IXGBE_DEV_ID_X550EM_A_KR_L:
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hw->phy.type = ixgbe_phy_x550em_kr;
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break;
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case IXGBE_DEV_ID_X550EM_X_1G_T:
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@@ -413,6 +423,121 @@ out:
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return ret;
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}
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+/**
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+ * ixgbe_get_phy_token - Get the token for shared PHY access
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+ * @hw: Pointer to hardware structure
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+ */
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+static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
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+{
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+ struct ixgbe_hic_phy_token_req token_cmd;
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+ s32 status;
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+
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+ token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
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+ token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
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+ token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
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+ token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
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+ token_cmd.port_number = hw->bus.lan_id;
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+ token_cmd.command_type = FW_PHY_TOKEN_REQ;
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+ token_cmd.pad = 0;
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+ status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
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+ IXGBE_HI_COMMAND_TIMEOUT,
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+ true);
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+ if (status)
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+ return status;
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+ if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
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+ return 0;
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+ if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
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+ return IXGBE_ERR_FW_RESP_INVALID;
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+
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+ return IXGBE_ERR_TOKEN_RETRY;
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+}
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+
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+/**
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+ * ixgbe_put_phy_token - Put the token for shared PHY access
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+ * @hw: Pointer to hardware structure
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+ */
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+static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
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+{
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+ struct ixgbe_hic_phy_token_req token_cmd;
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+ s32 status;
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+
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+ token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
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+ token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
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+ token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
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+ token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
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+ token_cmd.port_number = hw->bus.lan_id;
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+ token_cmd.command_type = FW_PHY_TOKEN_REL;
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+ token_cmd.pad = 0;
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+ status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
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+ IXGBE_HI_COMMAND_TIMEOUT,
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+ true);
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+ if (status)
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+ return status;
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+ if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
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+ return 0;
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+ return IXGBE_ERR_FW_RESP_INVALID;
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+}
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+
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+/**
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+ * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
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+ * @hw: pointer to hardware structure
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+ * @reg_addr: 32 bit PHY register to write
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+ * @device_type: 3 bit device type
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+ * @data: Data to write to the register
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+ **/
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+static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
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+ __always_unused u32 device_type,
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+ u32 data)
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+{
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+ struct ixgbe_hic_internal_phy_req write_cmd;
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+
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+ memset(&write_cmd, 0, sizeof(write_cmd));
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+ write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
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+ write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
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+ write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
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+ write_cmd.port_number = hw->bus.lan_id;
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+ write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
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+ write_cmd.address = cpu_to_be16(reg_addr);
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+ write_cmd.write_data = cpu_to_be32(data);
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+
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+ return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
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+ IXGBE_HI_COMMAND_TIMEOUT, false);
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+}
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+
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+/**
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+ * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
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+ * @hw: pointer to hardware structure
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+ * @reg_addr: 32 bit PHY register to write
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+ * @device_type: 3 bit device type
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+ * @data: Pointer to read data from the register
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+ **/
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+static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
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+ __always_unused u32 device_type,
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+ u32 *data)
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+{
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+ union {
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+ struct ixgbe_hic_internal_phy_req cmd;
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+ struct ixgbe_hic_internal_phy_resp rsp;
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+ } hic;
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+ s32 status;
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+
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+ memset(&hic, 0, sizeof(hic));
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+ hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
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+ hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
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+ hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
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+ hic.cmd.port_number = hw->bus.lan_id;
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+ hic.cmd.command_type = FW_INT_PHY_REQ_READ;
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+ hic.cmd.address = cpu_to_be16(reg_addr);
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+
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+ status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
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+ IXGBE_HI_COMMAND_TIMEOUT, true);
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+
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+ /* Extract the register value from the response. */
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+ *data = be32_to_cpu(hic.rsp.read_data);
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+
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+ return status;
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+}
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+
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/** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
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* command assuming that the semaphore is already obtained.
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* @hw: pointer to hardware structure
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@@ -437,8 +562,7 @@ static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
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/* one word */
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buffer.length = cpu_to_be16(sizeof(u16));
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- status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
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- sizeof(buffer),
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+ status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
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IXGBE_HI_COMMAND_TIMEOUT, false);
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if (status)
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return status;
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@@ -488,7 +612,7 @@ static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
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buffer.address = cpu_to_be32((offset + current_word) * 2);
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buffer.length = cpu_to_be16(words_to_read * 2);
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- status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
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+ status = ixgbe_host_interface_command(hw, &buffer,
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sizeof(buffer),
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IXGBE_HI_COMMAND_TIMEOUT,
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false);
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@@ -771,8 +895,7 @@ static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
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buffer.data = data;
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buffer.address = cpu_to_be32(offset * 2);
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- status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
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- sizeof(buffer),
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+ status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
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IXGBE_HI_COMMAND_TIMEOUT, false);
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return status;
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}
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@@ -814,8 +937,7 @@ static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
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buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
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buffer.req.checksum = FW_DEFAULT_CHECKSUM;
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- status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
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- sizeof(buffer),
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+ status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
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IXGBE_HI_COMMAND_TIMEOUT, false);
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return status;
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}
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@@ -862,9 +984,9 @@ static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
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fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
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fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
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fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
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- fw_cmd.port_number = (u8)hw->bus.lan_id;
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+ fw_cmd.port_number = hw->bus.lan_id;
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- status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
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+ status = ixgbe_host_interface_command(hw, &fw_cmd,
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sizeof(struct ixgbe_hic_disable_rxen),
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IXGBE_HI_COMMAND_TIMEOUT, true);
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@@ -1248,6 +1370,117 @@ i2c_err:
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return status;
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}
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+/**
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+ * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
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+ * @hw: pointer to hardware structure
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+ *
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+ * Configure the the integrated PHY for native SFP support.
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+ */
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+static s32
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+ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
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+ __always_unused bool autoneg_wait_to_complete)
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+{
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+ bool setup_linear = false;
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+ u32 reg_phy_int;
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+ s32 rc;
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+
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+ /* Check if SFP module is supported and linear */
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+ rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
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+
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+ /* If no SFP module present, then return success. Return success since
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+ * SFP not present error is not excepted in the setup MAC link flow.
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+ */
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+ if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
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+ return 0;
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+
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+ if (!rc)
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+ return rc;
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+
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+ /* Configure internal PHY for native SFI */
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+ rc = hw->mac.ops.read_iosf_sb_reg(hw,
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+ IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
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+ IXGBE_SB_IOSF_TARGET_KR_PHY,
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+ ®_phy_int);
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+ if (rc)
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+ return rc;
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+
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+ if (setup_linear) {
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+ reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
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+ reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
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+ } else {
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+ reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
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+ reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
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+ }
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+
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+ rc = hw->mac.ops.write_iosf_sb_reg(hw,
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+ IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
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+ IXGBE_SB_IOSF_TARGET_KR_PHY,
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+ reg_phy_int);
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+ if (rc)
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+ return rc;
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+
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+ /* Setup XFI/SFI internal link */
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+ return ixgbe_setup_ixfi_x550em(hw, &speed);
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+}
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+
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+/**
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+ * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
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+ * @hw: pointer to hardware structure
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+ *
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+ * Configure the the integrated PHY for SFP support.
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+ */
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+static s32
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+ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
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+ __always_unused bool autoneg_wait_to_complete)
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+{
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+ u32 reg_slice, slice_offset;
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+ bool setup_linear = false;
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+ u16 reg_phy_ext;
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+ s32 rc;
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+
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+ /* Check if SFP module is supported and linear */
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+ rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
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+
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+ /* If no SFP module present, then return success. Return success since
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+ * SFP not present error is not excepted in the setup MAC link flow.
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+ */
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+ if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
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+ return 0;
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+
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+ if (!rc)
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+ return rc;
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+
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+ /* Configure internal PHY for KR/KX. */
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+ ixgbe_setup_kr_speed_x550em(hw, speed);
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+
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+ if (!hw->phy.mdio.prtad || hw->phy.mdio.prtad == 0xFFFF)
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+ return IXGBE_ERR_PHY_ADDR_INVALID;
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+
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+ /* Get external PHY device id */
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+ rc = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
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+ IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
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+ if (rc)
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+ return rc;
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+
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+ /* When configuring quad port CS4223, the MAC instance is part
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+ * of the slice offset.
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+ */
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+ if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
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+ slice_offset = (hw->bus.lan_id +
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+ (hw->bus.instance_id << 1)) << 12;
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+ else
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+ slice_offset = hw->bus.lan_id << 12;
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+
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+ /* Configure CS4227/CS4223 LINE side to proper mode. */
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+ reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
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+ if (setup_linear)
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+ reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
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+ else
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+ reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
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+ return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,
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+ reg_phy_ext);
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+}
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+
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/**
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* ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
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* @hw: pointer to hardware structure
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@@ -1327,6 +1560,57 @@ static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
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return 0;
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}
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+/**
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+ * ixgbe_setup_sgmii - Set up link for sgmii
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+ * @hw: pointer to hardware structure
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+ */
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+static s32
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+ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
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+ __always_unused bool autoneg_wait_to_complete)
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|
+{
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+ struct ixgbe_mac_info *mac = &hw->mac;
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+ u32 lval, sval;
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+ s32 rc;
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+
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+ rc = mac->ops.read_iosf_sb_reg(hw,
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+ IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
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+ IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
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+ if (rc)
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+ return rc;
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+
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+ lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
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+ lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
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+ lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
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+ lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
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+ lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
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|
+ rc = mac->ops.write_iosf_sb_reg(hw,
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+ IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
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|
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+ IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
|
|
|
+ if (rc)
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|
|
+ return rc;
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|
|
+
|
|
|
+ rc = mac->ops.read_iosf_sb_reg(hw,
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|
|
+ IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
|
|
|
+ IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
|
|
|
+ if (rc)
|
|
|
+ return rc;
|
|
|
+
|
|
|
+ sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
|
|
|
+ sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
|
|
|
+ rc = mac->ops.write_iosf_sb_reg(hw,
|
|
|
+ IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
|
|
|
+ IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
|
|
|
+ if (rc)
|
|
|
+ return rc;
|
|
|
+
|
|
|
+ lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
|
|
|
+ rc = mac->ops.write_iosf_sb_reg(hw,
|
|
|
+ IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
|
|
|
+ IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
/** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
|
|
|
* @hw: pointer to hardware structure
|
|
|
**/
|
|
|
@@ -1344,7 +1628,19 @@ static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
|
|
|
mac->ops.flap_tx_laser = NULL;
|
|
|
mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
|
|
|
mac->ops.setup_fc = ixgbe_setup_fc_x550em;
|
|
|
- mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
|
|
|
+ switch (hw->device_id) {
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SFP_N:
|
|
|
+ mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
|
|
|
+ break;
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SFP:
|
|
|
+ mac->ops.setup_mac_link =
|
|
|
+ ixgbe_setup_mac_link_sfp_x550a;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ mac->ops.setup_mac_link =
|
|
|
+ ixgbe_setup_mac_link_sfp_x550em;
|
|
|
+ break;
|
|
|
+ }
|
|
|
mac->ops.set_rate_select_speed =
|
|
|
ixgbe_set_soft_rate_select_speed;
|
|
|
break;
|
|
|
@@ -1352,6 +1648,11 @@ static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
|
|
|
mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
|
|
|
mac->ops.setup_fc = ixgbe_setup_fc_generic;
|
|
|
mac->ops.check_link = ixgbe_check_link_t_X550em;
|
|
|
+ return;
|
|
|
+ case ixgbe_media_type_backplane:
|
|
|
+ if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
|
|
|
+ hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
|
|
|
+ mac->ops.setup_link = ixgbe_setup_sgmii;
|
|
|
break;
|
|
|
default:
|
|
|
mac->ops.setup_fc = ixgbe_setup_fc_x550em;
|
|
|
@@ -1618,7 +1919,7 @@ static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
|
|
|
s32 status;
|
|
|
u32 reg_val;
|
|
|
|
|
|
- status = ixgbe_read_iosf_sb_reg_x550(hw,
|
|
|
+ status = hw->mac.ops.read_iosf_sb_reg(hw,
|
|
|
IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
|
|
|
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
|
|
|
if (status)
|
|
|
@@ -1640,7 +1941,7 @@ static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
|
|
|
|
|
|
/* Restart auto-negotiation. */
|
|
|
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
|
|
|
- status = ixgbe_write_iosf_sb_reg_x550(hw,
|
|
|
+ status = hw->mac.ops.write_iosf_sb_reg(hw,
|
|
|
IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
|
|
|
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
|
|
|
|
|
|
@@ -1657,9 +1958,9 @@ static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
|
|
|
s32 status;
|
|
|
u32 reg_val;
|
|
|
|
|
|
- status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
|
|
|
- IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
|
|
|
- hw->bus.lan_id, ®_val);
|
|
|
+ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
|
|
|
+ IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
|
|
|
+ hw->bus.lan_id, ®_val);
|
|
|
if (status)
|
|
|
return status;
|
|
|
|
|
|
@@ -1678,20 +1979,24 @@ static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
|
|
|
|
|
|
/* Restart auto-negotiation. */
|
|
|
reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
|
|
|
- status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
|
|
|
- IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
|
|
|
- hw->bus.lan_id, reg_val);
|
|
|
+ status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
|
|
|
+ IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
|
|
|
+ hw->bus.lan_id, reg_val);
|
|
|
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
-/** ixgbe_setup_kr_x550em - Configure the KR PHY.
|
|
|
- * @hw: pointer to hardware structure
|
|
|
+/**
|
|
|
+ * ixgbe_setup_kr_x550em - Configure the KR PHY
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
*
|
|
|
- * Configures the integrated KR PHY.
|
|
|
+ * Configures the integrated KR PHY for X550EM_x.
|
|
|
**/
|
|
|
static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
|
|
|
{
|
|
|
+ if (hw->mac.type != ixgbe_mac_X550EM_x)
|
|
|
+ return 0;
|
|
|
+
|
|
|
return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
|
|
|
}
|
|
|
|
|
|
@@ -1897,12 +2202,15 @@ static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
|
|
|
return IXGBE_ERR_CONFIG;
|
|
|
}
|
|
|
|
|
|
- if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
|
|
|
+ if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR &&
|
|
|
+ hw->device_id != IXGBE_DEV_ID_X550EM_A_KR &&
|
|
|
+ hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L)
|
|
|
return 0;
|
|
|
|
|
|
- rc = ixgbe_read_iosf_sb_reg_x550(hw,
|
|
|
- IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
|
|
|
- IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
|
|
|
+ rc = hw->mac.ops.read_iosf_sb_reg(hw,
|
|
|
+ IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
|
|
|
+ IXGBE_SB_IOSF_TARGET_KR_PHY,
|
|
|
+ ®_val);
|
|
|
if (rc)
|
|
|
return rc;
|
|
|
|
|
|
@@ -1912,9 +2220,10 @@ static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
|
|
|
reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
|
|
|
if (asm_dir)
|
|
|
reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
|
|
|
- rc = ixgbe_write_iosf_sb_reg_x550(hw,
|
|
|
- IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
|
|
|
- IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
|
|
|
+ rc = hw->mac.ops.write_iosf_sb_reg(hw,
|
|
|
+ IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
|
|
|
+ IXGBE_SB_IOSF_TARGET_KR_PHY,
|
|
|
+ reg_val);
|
|
|
|
|
|
/* This device does not fully support AN. */
|
|
|
hw->fc.disable_fc_autoneg = true;
|
|
|
@@ -2019,6 +2328,36 @@ static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
+/**
|
|
|
+ * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ *
|
|
|
+ * Read NW_MNG_IF_SEL register and save field values.
|
|
|
+ */
|
|
|
+static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
|
|
|
+{
|
|
|
+ /* Save NW management interface connected on board. This is used
|
|
|
+ * to determine internal PHY mode.
|
|
|
+ */
|
|
|
+ hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
|
|
|
+
|
|
|
+ /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
|
|
|
+ * PHY address. This register field was has only been used for X552.
|
|
|
+ */
|
|
|
+ if (!hw->phy.nw_mng_if_sel) {
|
|
|
+ if (hw->mac.type == ixgbe_mac_x550em_a) {
|
|
|
+ struct ixgbe_adapter *adapter = hw->back;
|
|
|
+
|
|
|
+ e_warn(drv, "nw_mng_if_sel not set\n");
|
|
|
+ }
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
|
|
|
+ IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
|
|
|
+ IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
|
|
|
+}
|
|
|
+
|
|
|
/** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
|
|
|
* @hw: pointer to hardware structure
|
|
|
*
|
|
|
@@ -2033,14 +2372,11 @@ static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
|
|
|
|
|
|
hw->mac.ops.set_lan_id(hw);
|
|
|
|
|
|
+ ixgbe_read_mng_if_sel_x550em(hw);
|
|
|
+
|
|
|
if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
|
|
|
phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
|
|
|
ixgbe_setup_mux_ctl(hw);
|
|
|
-
|
|
|
- /* Save NW management interface connected on board. This is used
|
|
|
- * to determine internal PHY mode.
|
|
|
- */
|
|
|
- phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
|
|
|
}
|
|
|
|
|
|
/* Identify the PHY or SFP module */
|
|
|
@@ -2103,16 +2439,24 @@ static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
|
|
|
|
|
|
/* Detect if there is a copper PHY attached. */
|
|
|
switch (hw->device_id) {
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SGMII:
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SGMII_L:
|
|
|
+ hw->phy.type = ixgbe_phy_sgmii;
|
|
|
+ /* Fallthrough */
|
|
|
case IXGBE_DEV_ID_X550EM_X_KR:
|
|
|
case IXGBE_DEV_ID_X550EM_X_KX4:
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_KR:
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_KR_L:
|
|
|
media_type = ixgbe_media_type_backplane;
|
|
|
break;
|
|
|
case IXGBE_DEV_ID_X550EM_X_SFP:
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SFP:
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SFP_N:
|
|
|
media_type = ixgbe_media_type_fiber;
|
|
|
break;
|
|
|
case IXGBE_DEV_ID_X550EM_X_1G_T:
|
|
|
case IXGBE_DEV_ID_X550EM_X_10G_T:
|
|
|
- media_type = ixgbe_media_type_copper;
|
|
|
+ media_type = ixgbe_media_type_copper;
|
|
|
break;
|
|
|
default:
|
|
|
media_type = ixgbe_media_type_unknown;
|
|
|
@@ -2160,6 +2504,27 @@ static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
+/**
|
|
|
+ * ixgbe_set_mdio_speed - Set MDIO clock speed
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ */
|
|
|
+static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
|
|
|
+{
|
|
|
+ u32 hlreg0;
|
|
|
+
|
|
|
+ switch (hw->device_id) {
|
|
|
+ case IXGBE_DEV_ID_X550EM_X_10G_T:
|
|
|
+ case IXGBE_DEV_ID_X550EM_A_SFP:
|
|
|
+ /* Config MDIO clock speed before the first MDIO PHY access */
|
|
|
+ hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
|
|
|
+ hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
/** ixgbe_reset_hw_X550em - Perform hardware reset
|
|
|
** @hw: pointer to hardware structure
|
|
|
**
|
|
|
@@ -2173,7 +2538,6 @@ static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
|
|
|
s32 status;
|
|
|
u32 ctrl = 0;
|
|
|
u32 i;
|
|
|
- u32 hlreg0;
|
|
|
bool link_up = false;
|
|
|
|
|
|
/* Call adapter stop to disable Tx/Rx and clear interrupts */
|
|
|
@@ -2259,11 +2623,7 @@ mac_reset_top:
|
|
|
hw->mac.num_rar_entries = 128;
|
|
|
hw->mac.ops.init_rx_addrs(hw);
|
|
|
|
|
|
- if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
|
|
|
- hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
|
|
|
- hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
|
|
|
- }
|
|
|
+ ixgbe_set_mdio_speed(hw);
|
|
|
|
|
|
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
|
|
|
ixgbe_setup_mux_ctl(hw);
|
|
|
@@ -2376,6 +2736,110 @@ static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
|
|
|
ixgbe_release_swfw_sync_X540(hw, mask);
|
|
|
}
|
|
|
|
|
|
+/**
|
|
|
+ * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @mask: Mask to specify which semaphore to acquire
|
|
|
+ *
|
|
|
+ * Acquires the SWFW semaphore and get the shared PHY token as needed
|
|
|
+ */
|
|
|
+static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
|
|
|
+{
|
|
|
+ u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
|
|
|
+ int retries = FW_PHY_TOKEN_RETRIES;
|
|
|
+ s32 status;
|
|
|
+
|
|
|
+ while (--retries) {
|
|
|
+ status = 0;
|
|
|
+ if (hmask)
|
|
|
+ status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
|
|
|
+ if (status)
|
|
|
+ return status;
|
|
|
+ if (!(mask & IXGBE_GSSR_TOKEN_SM))
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ status = ixgbe_get_phy_token(hw);
|
|
|
+ if (!status)
|
|
|
+ return 0;
|
|
|
+ if (hmask)
|
|
|
+ ixgbe_release_swfw_sync_X540(hw, hmask);
|
|
|
+ if (status != IXGBE_ERR_TOKEN_RETRY)
|
|
|
+ return status;
|
|
|
+ udelay(FW_PHY_TOKEN_DELAY * 1000);
|
|
|
+ }
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @mask: Mask to specify which semaphore to release
|
|
|
+ *
|
|
|
+ * Release the SWFW semaphore and puts the shared PHY token as needed
|
|
|
+ */
|
|
|
+static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
|
|
|
+{
|
|
|
+ u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
|
|
|
+
|
|
|
+ if (mask & IXGBE_GSSR_TOKEN_SM)
|
|
|
+ ixgbe_put_phy_token(hw);
|
|
|
+
|
|
|
+ if (hmask)
|
|
|
+ ixgbe_release_swfw_sync_X540(hw, hmask);
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ixgbe_read_phy_reg_x550a - Reads specified PHY register
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @reg_addr: 32 bit address of PHY register to read
|
|
|
+ * @phy_data: Pointer to read data from PHY register
|
|
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+ *
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+ * Reads a value from a specified PHY register using the SWFW lock and PHY
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+ * Token. The PHY Token is needed since the MDIO is shared between to MAC
|
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+ * instances.
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+ */
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+static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
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|
|
+ u32 device_type, u16 *phy_data)
|
|
|
+{
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+ u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
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+ s32 status;
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+
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+ if (hw->mac.ops.acquire_swfw_sync(hw, mask))
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|
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+ return IXGBE_ERR_SWFW_SYNC;
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+
|
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+ status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
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+
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+ hw->mac.ops.release_swfw_sync(hw, mask);
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+
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+ return status;
|
|
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+}
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+
|
|
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+/**
|
|
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+ * ixgbe_write_phy_reg_x550a - Writes specified PHY register
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @reg_addr: 32 bit PHY register to write
|
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+ * @device_type: 5 bit device type
|
|
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+ * @phy_data: Data to write to the PHY register
|
|
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+ *
|
|
|
+ * Writes a value to specified PHY register using the SWFW lock and PHY Token.
|
|
|
+ * The PHY Token is needed since the MDIO is shared between to MAC instances.
|
|
|
+ */
|
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|
+static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
|
|
|
+ u32 device_type, u16 phy_data)
|
|
|
+{
|
|
|
+ u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
|
|
|
+ s32 status;
|
|
|
+
|
|
|
+ if (hw->mac.ops.acquire_swfw_sync(hw, mask))
|
|
|
+ return IXGBE_ERR_SWFW_SYNC;
|
|
|
+
|
|
|
+ status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
|
|
|
+ hw->mac.ops.release_swfw_sync(hw, mask);
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
#define X550_COMMON_MAC \
|
|
|
.init_hw = &ixgbe_init_hw_generic, \
|
|
|
.start_hw = &ixgbe_start_hw_X540, \
|
|
|
@@ -2452,6 +2916,25 @@ static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
|
|
|
.release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
|
|
|
.init_swfw_sync = &ixgbe_init_swfw_sync_X540,
|
|
|
.setup_fc = NULL, /* defined later */
|
|
|
+ .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
|
|
|
+ .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
|
|
|
+};
|
|
|
+
|
|
|
+static struct ixgbe_mac_operations mac_ops_x550em_a = {
|
|
|
+ X550_COMMON_MAC
|
|
|
+ .reset_hw = ixgbe_reset_hw_X550em,
|
|
|
+ .get_media_type = ixgbe_get_media_type_X550em,
|
|
|
+ .get_san_mac_addr = NULL,
|
|
|
+ .get_wwn_prefix = NULL,
|
|
|
+ .setup_link = NULL, /* defined later */
|
|
|
+ .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
|
|
|
+ .get_bus_info = ixgbe_get_bus_info_X550em,
|
|
|
+ .setup_sfp = ixgbe_setup_sfp_modules_X550em,
|
|
|
+ .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
|
|
|
+ .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
|
|
|
+ .setup_fc = ixgbe_setup_fc_generic,
|
|
|
+ .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
|
|
|
+ .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
|
|
|
};
|
|
|
|
|
|
#define X550_COMMON_EEP \
|
|
|
@@ -2482,8 +2965,6 @@ static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
|
|
|
.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
|
|
|
.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
|
|
|
.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
|
|
|
- .read_reg = &ixgbe_read_phy_reg_generic, \
|
|
|
- .write_reg = &ixgbe_write_phy_reg_generic, \
|
|
|
.setup_link = &ixgbe_setup_phy_link_generic, \
|
|
|
.set_phy_power = NULL, \
|
|
|
.check_overtemp = &ixgbe_tn_check_overtemp, \
|
|
|
@@ -2493,12 +2974,16 @@ static const struct ixgbe_phy_operations phy_ops_X550 = {
|
|
|
X550_COMMON_PHY
|
|
|
.init = NULL,
|
|
|
.identify = &ixgbe_identify_phy_generic,
|
|
|
+ .read_reg = &ixgbe_read_phy_reg_generic,
|
|
|
+ .write_reg = &ixgbe_write_phy_reg_generic,
|
|
|
};
|
|
|
|
|
|
static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
|
|
|
X550_COMMON_PHY
|
|
|
.init = &ixgbe_init_phy_ops_X550em,
|
|
|
.identify = &ixgbe_identify_phy_x550em,
|
|
|
+ .read_reg = &ixgbe_read_phy_reg_generic,
|
|
|
+ .write_reg = &ixgbe_write_phy_reg_generic,
|
|
|
.read_i2c_combined = &ixgbe_read_i2c_combined_generic,
|
|
|
.write_i2c_combined = &ixgbe_write_i2c_combined_generic,
|
|
|
.read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
|
|
|
@@ -2506,6 +2991,14 @@ static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
|
|
|
&ixgbe_write_i2c_combined_generic_unlocked,
|
|
|
};
|
|
|
|
|
|
+static const struct ixgbe_phy_operations phy_ops_x550em_a = {
|
|
|
+ X550_COMMON_PHY
|
|
|
+ .init = &ixgbe_init_phy_ops_X550em,
|
|
|
+ .identify = &ixgbe_identify_phy_x550em,
|
|
|
+ .read_reg = &ixgbe_read_phy_reg_x550a,
|
|
|
+ .write_reg = &ixgbe_write_phy_reg_x550a,
|
|
|
+};
|
|
|
+
|
|
|
static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
|
|
|
IXGBE_MVALS_INIT(X550)
|
|
|
};
|
|
|
@@ -2514,6 +3007,10 @@ static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
|
|
|
IXGBE_MVALS_INIT(X550EM_x)
|
|
|
};
|
|
|
|
|
|
+static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
|
|
|
+ IXGBE_MVALS_INIT(X550EM_a)
|
|
|
+};
|
|
|
+
|
|
|
const struct ixgbe_info ixgbe_X550_info = {
|
|
|
.mac = ixgbe_mac_X550,
|
|
|
.get_invariants = &ixgbe_get_invariants_X540,
|
|
|
@@ -2533,3 +3030,13 @@ const struct ixgbe_info ixgbe_X550EM_x_info = {
|
|
|
.mbx_ops = &mbx_ops_generic,
|
|
|
.mvals = ixgbe_mvals_X550EM_x,
|
|
|
};
|
|
|
+
|
|
|
+const struct ixgbe_info ixgbe_x550em_a_info = {
|
|
|
+ .mac = ixgbe_mac_x550em_a,
|
|
|
+ .get_invariants = &ixgbe_get_invariants_X550_x,
|
|
|
+ .mac_ops = &mac_ops_x550em_a,
|
|
|
+ .eeprom_ops = &eeprom_ops_X550EM_x,
|
|
|
+ .phy_ops = &phy_ops_x550em_a,
|
|
|
+ .mbx_ops = &mbx_ops_generic,
|
|
|
+ .mvals = ixgbe_mvals_x550em_a,
|
|
|
+};
|
David S. Miller