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@@ -184,19 +184,18 @@ static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
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* system memory <-> ACP SRAM
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* system memory <-> ACP SRAM
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*/
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*/
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static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
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static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
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- u32 size, int direction,
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- u32 pte_offset, u32 asic_type)
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+ u32 size, int direction, u32 pte_offset,
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+ u16 ch, u32 sram_bank,
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+ u16 dma_dscr_idx, u32 asic_type)
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{
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{
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u16 i;
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u16 i;
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- u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
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acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
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acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
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for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
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for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
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dmadscr[i].xfer_val = 0;
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dmadscr[i].xfer_val = 0;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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- dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i;
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- dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS
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- + (i * (size/2));
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+ dma_dscr_idx = dma_dscr_idx + i;
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+ dmadscr[i].dest = sram_bank + (i * (size/2));
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dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
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dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
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+ (pte_offset * SZ_4K) + (i * (size/2));
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+ (pte_offset * SZ_4K) + (i * (size/2));
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switch (asic_type) {
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switch (asic_type) {
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@@ -211,25 +210,19 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
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(size / 2);
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(size / 2);
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}
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}
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} else {
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} else {
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- dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
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+ dma_dscr_idx = dma_dscr_idx + i;
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+ dmadscr[i].src = sram_bank + (i * (size/2));
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+ dmadscr[i].dest =
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+ ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
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+ (pte_offset * SZ_4K) + (i * (size/2));
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switch (asic_type) {
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switch (asic_type) {
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case CHIP_STONEY:
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case CHIP_STONEY:
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- dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS +
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- (i * (size/2));
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- dmadscr[i].dest =
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- ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
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- (pte_offset * SZ_4K) + (i * (size/2));
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dmadscr[i].xfer_val |=
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dmadscr[i].xfer_val |=
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BIT(22) |
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BIT(22) |
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(ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) |
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(ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) |
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(size / 2);
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(size / 2);
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break;
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break;
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default:
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default:
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- dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
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- (i * (size/2));
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- dmadscr[i].dest =
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- ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
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- (pte_offset * SZ_4K) + (i * (size/2));
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dmadscr[i].xfer_val |=
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dmadscr[i].xfer_val |=
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BIT(22) |
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BIT(22) |
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(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
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(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
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@@ -239,72 +232,49 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
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config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
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config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
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&dmadscr[i]);
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&dmadscr[i]);
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}
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}
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- if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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- config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM,
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- PLAYBACK_START_DMA_DESCR_CH12,
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- NUM_DSCRS_PER_CHANNEL,
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- ACP_DMA_PRIORITY_LEVEL_NORMAL);
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- else
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- config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM,
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- CAPTURE_START_DMA_DESCR_CH14,
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- NUM_DSCRS_PER_CHANNEL,
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- ACP_DMA_PRIORITY_LEVEL_NORMAL);
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+ config_acp_dma_channel(acp_mmio, ch,
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+ dma_dscr_idx - 1,
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+ NUM_DSCRS_PER_CHANNEL,
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+ ACP_DMA_PRIORITY_LEVEL_NORMAL);
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}
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}
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/* Initialize the DMA descriptor information for transfer between
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/* Initialize the DMA descriptor information for transfer between
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* ACP SRAM <-> I2S
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* ACP SRAM <-> I2S
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*/
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*/
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-static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
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- u32 size, int direction,
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- u32 asic_type)
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+static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
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+ int direction, u32 sram_bank,
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+ u16 destination, u16 ch,
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+ u16 dma_dscr_idx, u32 asic_type)
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{
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{
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u16 i;
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u16 i;
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- u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
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acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
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acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
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for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
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for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
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dmadscr[i].xfer_val = 0;
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dmadscr[i].xfer_val = 0;
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
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- dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i;
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- dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS +
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- (i * (size/2));
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+ dma_dscr_idx = dma_dscr_idx + i;
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+ dmadscr[i].src = sram_bank + (i * (size/2));
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/* dmadscr[i].dest is unused by hardware. */
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/* dmadscr[i].dest is unused by hardware. */
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dmadscr[i].dest = 0;
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dmadscr[i].dest = 0;
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- dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) |
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+ dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
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(size / 2);
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(size / 2);
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} else {
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} else {
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- dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i;
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+ dma_dscr_idx = dma_dscr_idx + i;
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/* dmadscr[i].src is unused by hardware. */
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/* dmadscr[i].src is unused by hardware. */
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dmadscr[i].src = 0;
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dmadscr[i].src = 0;
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- switch (asic_type) {
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- case CHIP_STONEY:
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- dmadscr[i].dest =
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- ACP_SHARED_RAM_BANK_3_ADDRESS +
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- (i * (size / 2));
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- break;
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- default:
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- dmadscr[i].dest =
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- ACP_SHARED_RAM_BANK_5_ADDRESS +
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- (i * (size / 2));
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- }
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+ dmadscr[i].dest =
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+ sram_bank + (i * (size / 2));
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dmadscr[i].xfer_val |= BIT(22) |
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dmadscr[i].xfer_val |= BIT(22) |
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- (FROM_ACP_I2S_1 << 16) | (size / 2);
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+ (destination << 16) | (size / 2);
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}
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}
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config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
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config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
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&dmadscr[i]);
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&dmadscr[i]);
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}
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}
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/* Configure the DMA channel with the above descriptore */
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/* Configure the DMA channel with the above descriptore */
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- if (direction == SNDRV_PCM_STREAM_PLAYBACK)
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- config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
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- PLAYBACK_START_DMA_DESCR_CH13,
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- NUM_DSCRS_PER_CHANNEL,
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- ACP_DMA_PRIORITY_LEVEL_NORMAL);
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- else
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- config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
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- CAPTURE_START_DMA_DESCR_CH15,
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- NUM_DSCRS_PER_CHANNEL,
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- ACP_DMA_PRIORITY_LEVEL_NORMAL);
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+ config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
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+ NUM_DSCRS_PER_CHANNEL,
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+ ACP_DMA_PRIORITY_LEVEL_NORMAL);
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}
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}
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/* Create page table entries in ACP SRAM for the allocated memory */
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/* Create page table entries in ACP SRAM for the allocated memory */
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@@ -346,23 +316,51 @@ static void config_acp_dma(void __iomem *acp_mmio,
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struct audio_substream_data *audio_config,
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struct audio_substream_data *audio_config,
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u32 asic_type)
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u32 asic_type)
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{
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{
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- u32 pte_offset;
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+ u32 pte_offset, sram_bank;
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+ u16 ch1, ch2, destination, dma_dscr_idx;
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- if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
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+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) {
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pte_offset = ACP_PLAYBACK_PTE_OFFSET;
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pte_offset = ACP_PLAYBACK_PTE_OFFSET;
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- else
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+ ch1 = SYSRAM_TO_ACP_CH_NUM;
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+ ch2 = ACP_TO_I2S_DMA_CH_NUM;
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+ sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS;
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+ destination = TO_ACP_I2S_1;
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+
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+ } else {
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pte_offset = ACP_CAPTURE_PTE_OFFSET;
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pte_offset = ACP_CAPTURE_PTE_OFFSET;
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+ ch1 = SYSRAM_TO_ACP_CH_NUM;
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+ ch2 = ACP_TO_I2S_DMA_CH_NUM;
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+ switch (asic_type) {
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+ case CHIP_STONEY:
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+ sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS;
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+ break;
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+ default:
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+ sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS;
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+ }
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+ destination = FROM_ACP_I2S_1;
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+ }
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acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages,
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acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages,
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pte_offset);
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pte_offset);
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+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
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+ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
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+ else
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+ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
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/* Configure System memory <-> ACP SRAM DMA descriptors */
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/* Configure System memory <-> ACP SRAM DMA descriptors */
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set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,
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set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,
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- audio_config->direction, pte_offset, asic_type);
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+ audio_config->direction, pte_offset,
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+ ch1, sram_bank, dma_dscr_idx, asic_type);
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+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
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+ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
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+ else
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+ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15;
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/* Configure ACP SRAM <-> I2S DMA descriptors */
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/* Configure ACP SRAM <-> I2S DMA descriptors */
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set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size,
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set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size,
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- audio_config->direction, asic_type);
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+ audio_config->direction, sram_bank,
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+ destination, ch2, dma_dscr_idx,
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+ asic_type);
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}
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}
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/* Start a given DMA channel transfer */
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/* Start a given DMA channel transfer */
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@@ -657,7 +655,7 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
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1, 0);
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1, 0);
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acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
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acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
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- snd_pcm_period_elapsed(irq_data->play_stream);
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+ snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
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acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
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acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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@@ -680,7 +678,7 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
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if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
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if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
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valid_irq = true;
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valid_irq = true;
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- snd_pcm_period_elapsed(irq_data->capture_stream);
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+ snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
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acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
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acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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}
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@@ -738,11 +736,11 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
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* This enablement is not required for another stream, if current
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* This enablement is not required for another stream, if current
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* stream is not closed
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* stream is not closed
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*/
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*/
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- if (!intr_data->play_stream && !intr_data->capture_stream)
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+ if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream)
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acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
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acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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- intr_data->play_stream = substream;
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+ intr_data->play_i2ssp_stream = substream;
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/* For Stoney, Memory gating is disabled,i.e SRAM Banks
|
|
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
|
|
|
* won't be turned off. The default state for SRAM banks is ON.
|
|
* won't be turned off. The default state for SRAM banks is ON.
|
|
|
* Setting SRAM bank state code skipped for STONEY platform.
|
|
* Setting SRAM bank state code skipped for STONEY platform.
|
|
@@ -753,7 +751,7 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
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|
|
bank, true);
|
|
bank, true);
|
|
|
}
|
|
}
|
|
|
} else {
|
|
} else {
|
|
|
- intr_data->capture_stream = substream;
|
|
|
|
|
|
|
+ intr_data->capture_i2ssp_stream = substream;
|
|
|
if (intr_data->asic_type != CHIP_STONEY) {
|
|
if (intr_data->asic_type != CHIP_STONEY) {
|
|
|
for (bank = 5; bank <= 8; bank++)
|
|
for (bank = 5; bank <= 8; bank++)
|
|
|
acp_set_sram_bank_state(intr_data->acp_mmio,
|
|
acp_set_sram_bank_state(intr_data->acp_mmio,
|
|
@@ -862,11 +860,11 @@ static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
|
|
|
bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream);
|
|
bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream);
|
|
|
|
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
- if (bytescount > rtd->renderbytescount)
|
|
|
|
|
- bytescount = bytescount - rtd->renderbytescount;
|
|
|
|
|
|
|
+ if (bytescount > rtd->i2ssp_renderbytescount)
|
|
|
|
|
+ bytescount = bytescount - rtd->i2ssp_renderbytescount;
|
|
|
} else {
|
|
} else {
|
|
|
- if (bytescount > rtd->capturebytescount)
|
|
|
|
|
- bytescount = bytescount - rtd->capturebytescount;
|
|
|
|
|
|
|
+ if (bytescount > rtd->i2ssp_capturebytescount)
|
|
|
|
|
+ bytescount = bytescount - rtd->i2ssp_capturebytescount;
|
|
|
}
|
|
}
|
|
|
pos = do_div(bytescount, buffersize);
|
|
pos = do_div(bytescount, buffersize);
|
|
|
return bytes_to_frames(runtime, pos);
|
|
return bytes_to_frames(runtime, pos);
|
|
@@ -923,8 +921,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
bytescount = acp_get_byte_count(rtd->acp_mmio,
|
|
bytescount = acp_get_byte_count(rtd->acp_mmio,
|
|
|
substream->stream);
|
|
substream->stream);
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
- if (rtd->renderbytescount == 0)
|
|
|
|
|
- rtd->renderbytescount = bytescount;
|
|
|
|
|
|
|
+ if (rtd->i2ssp_renderbytescount == 0)
|
|
|
|
|
+ rtd->i2ssp_renderbytescount = bytescount;
|
|
|
acp_dma_start(rtd->acp_mmio,
|
|
acp_dma_start(rtd->acp_mmio,
|
|
|
SYSRAM_TO_ACP_CH_NUM, false);
|
|
SYSRAM_TO_ACP_CH_NUM, false);
|
|
|
while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
|
|
while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
|
|
@@ -941,8 +939,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
ACP_TO_I2S_DMA_CH_NUM, true);
|
|
ACP_TO_I2S_DMA_CH_NUM, true);
|
|
|
|
|
|
|
|
} else {
|
|
} else {
|
|
|
- if (rtd->capturebytescount == 0)
|
|
|
|
|
- rtd->capturebytescount = bytescount;
|
|
|
|
|
|
|
+ if (rtd->i2ssp_capturebytescount == 0)
|
|
|
|
|
+ rtd->i2ssp_capturebytescount = bytescount;
|
|
|
acp_dma_start(rtd->acp_mmio,
|
|
acp_dma_start(rtd->acp_mmio,
|
|
|
I2S_TO_ACP_DMA_CH_NUM, true);
|
|
I2S_TO_ACP_DMA_CH_NUM, true);
|
|
|
}
|
|
}
|
|
@@ -957,13 +955,17 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
* completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
|
|
* completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
|
|
|
*/
|
|
*/
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
|
+ ret = acp_dma_stop(rtd->acp_mmio,
|
|
|
|
|
+ SYSRAM_TO_ACP_CH_NUM);
|
|
|
ret = acp_dma_stop(rtd->acp_mmio,
|
|
ret = acp_dma_stop(rtd->acp_mmio,
|
|
|
ACP_TO_I2S_DMA_CH_NUM);
|
|
ACP_TO_I2S_DMA_CH_NUM);
|
|
|
- rtd->renderbytescount = 0;
|
|
|
|
|
|
|
+ rtd->i2ssp_renderbytescount = 0;
|
|
|
} else {
|
|
} else {
|
|
|
ret = acp_dma_stop(rtd->acp_mmio,
|
|
ret = acp_dma_stop(rtd->acp_mmio,
|
|
|
I2S_TO_ACP_DMA_CH_NUM);
|
|
I2S_TO_ACP_DMA_CH_NUM);
|
|
|
- rtd->capturebytescount = 0;
|
|
|
|
|
|
|
+ ret = acp_dma_stop(rtd->acp_mmio,
|
|
|
|
|
+ ACP_TO_SYSRAM_CH_NUM);
|
|
|
|
|
+ rtd->i2ssp_capturebytescount = 0;
|
|
|
}
|
|
}
|
|
|
break;
|
|
break;
|
|
|
default:
|
|
default:
|
|
@@ -1011,7 +1013,7 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
|
|
|
kfree(rtd);
|
|
kfree(rtd);
|
|
|
|
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
- adata->play_stream = NULL;
|
|
|
|
|
|
|
+ adata->play_i2ssp_stream = NULL;
|
|
|
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
|
|
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
|
|
|
* won't be turned off. The default state for SRAM banks is ON.
|
|
* won't be turned off. The default state for SRAM banks is ON.
|
|
|
* Setting SRAM bank state code skipped for STONEY platform.
|
|
* Setting SRAM bank state code skipped for STONEY platform.
|
|
@@ -1023,7 +1025,7 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
|
|
|
false);
|
|
false);
|
|
|
}
|
|
}
|
|
|
} else {
|
|
} else {
|
|
|
- adata->capture_stream = NULL;
|
|
|
|
|
|
|
+ adata->capture_i2ssp_stream = NULL;
|
|
|
if (adata->asic_type != CHIP_STONEY) {
|
|
if (adata->asic_type != CHIP_STONEY) {
|
|
|
for (bank = 5; bank <= 8; bank++)
|
|
for (bank = 5; bank <= 8; bank++)
|
|
|
acp_set_sram_bank_state(adata->acp_mmio, bank,
|
|
acp_set_sram_bank_state(adata->acp_mmio, bank,
|
|
@@ -1034,7 +1036,7 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
|
|
|
/* Disable ACP irq, when the current stream is being closed and
|
|
/* Disable ACP irq, when the current stream is being closed and
|
|
|
* another stream is also not active.
|
|
* another stream is also not active.
|
|
|
*/
|
|
*/
|
|
|
- if (!adata->play_stream && !adata->capture_stream)
|
|
|
|
|
|
|
+ if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream)
|
|
|
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
|
|
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
|
|
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
@@ -1085,8 +1087,9 @@ static int acp_audio_probe(struct platform_device *pdev)
|
|
|
* and device doesn't generate any interrupts.
|
|
* and device doesn't generate any interrupts.
|
|
|
*/
|
|
*/
|
|
|
|
|
|
|
|
- audio_drv_data->play_stream = NULL;
|
|
|
|
|
- audio_drv_data->capture_stream = NULL;
|
|
|
|
|
|
|
+ audio_drv_data->play_i2ssp_stream = NULL;
|
|
|
|
|
+ audio_drv_data->capture_i2ssp_stream = NULL;
|
|
|
|
|
+
|
|
|
audio_drv_data->asic_type = *pdata;
|
|
audio_drv_data->asic_type = *pdata;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
@@ -1150,7 +1153,7 @@ static int acp_pcm_resume(struct device *dev)
|
|
|
return status;
|
|
return status;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- if (adata->play_stream && adata->play_stream->runtime) {
|
|
|
|
|
|
|
+ if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
|
|
|
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
|
|
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
|
|
|
* won't be turned off. The default state for SRAM banks is ON.
|
|
* won't be turned off. The default state for SRAM banks is ON.
|
|
|
* Setting SRAM bank state code skipped for STONEY platform.
|
|
* Setting SRAM bank state code skipped for STONEY platform.
|
|
@@ -1161,17 +1164,17 @@ static int acp_pcm_resume(struct device *dev)
|
|
|
true);
|
|
true);
|
|
|
}
|
|
}
|
|
|
config_acp_dma(adata->acp_mmio,
|
|
config_acp_dma(adata->acp_mmio,
|
|
|
- adata->play_stream->runtime->private_data,
|
|
|
|
|
|
|
+ adata->play_i2ssp_stream->runtime->private_data,
|
|
|
adata->asic_type);
|
|
adata->asic_type);
|
|
|
}
|
|
}
|
|
|
- if (adata->capture_stream && adata->capture_stream->runtime) {
|
|
|
|
|
|
|
+ if (adata->capture_i2ssp_stream && adata->capture_i2ssp_stream->runtime) {
|
|
|
if (adata->asic_type != CHIP_STONEY) {
|
|
if (adata->asic_type != CHIP_STONEY) {
|
|
|
for (bank = 5; bank <= 8; bank++)
|
|
for (bank = 5; bank <= 8; bank++)
|
|
|
acp_set_sram_bank_state(adata->acp_mmio, bank,
|
|
acp_set_sram_bank_state(adata->acp_mmio, bank,
|
|
|
true);
|
|
true);
|
|
|
}
|
|
}
|
|
|
config_acp_dma(adata->acp_mmio,
|
|
config_acp_dma(adata->acp_mmio,
|
|
|
- adata->capture_stream->runtime->private_data,
|
|
|
|
|
|
|
+ adata->capture_i2ssp_stream->runtime->private_data,
|
|
|
adata->asic_type);
|
|
adata->asic_type);
|
|
|
}
|
|
}
|
|
|
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
|
|
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
|