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@@ -18,6 +18,22 @@
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#include "clk.h"
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#include "common.h"
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+#define CCSR 0xc
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+#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
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+#define CACRR 0x10
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+#define CDHIPR 0x48
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+#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
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+#define ARM_WAIT_DIV_396M 2
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+#define ARM_WAIT_DIV_792M 4
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+#define ARM_WAIT_DIV_996M 6
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+
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+#define PLL_ARM 0x0
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+#define BM_PLL_ARM_DIV_SELECT (0x7f << 0)
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+#define BM_PLL_ARM_POWERDOWN (1 << 12)
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+#define BM_PLL_ARM_ENABLE (1 << 13)
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+#define BM_PLL_ARM_LOCK (1 << 31)
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+#define PLL_ARM_DIV_792M 66
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+
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static const char *step_sels[] = { "osc", "pll2_pfd2", };
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static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
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static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
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@@ -65,6 +81,8 @@ static struct clk_div_table video_div_table[] = {
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static struct clk *clks[IMX6SL_CLK_END];
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static struct clk_onecell_data clk_data;
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+static void __iomem *ccm_base;
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+static void __iomem *anatop_base;
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static const u32 clks_init_on[] __initconst = {
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IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
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@@ -81,19 +99,70 @@ static const u32 clks_init_on[] __initconst = {
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* entering WAIT mode.
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*
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* This function will set the ARM clk to max value within the 12:5 limit.
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+ * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
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+ * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
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+ * the clk APIs can NOT be called in idle thread(may cause kernel schedule
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+ * as there is sleep function in PLL wait function), so here we just slow
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+ * down ARM to below freq according to previous freq:
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+ *
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+ * run mode wait mode
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+ * 396MHz -> 132MHz;
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+ * 792MHz -> 158.4MHz;
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+ * 996MHz -> 142.3MHz;
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*/
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+static int imx6sl_get_arm_divider_for_wait(void)
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+{
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+ if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
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+ return ARM_WAIT_DIV_396M;
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+ } else {
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+ if ((readl_relaxed(anatop_base + PLL_ARM) &
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+ BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
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+ return ARM_WAIT_DIV_792M;
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+ else
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+ return ARM_WAIT_DIV_996M;
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+ }
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+}
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+
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+static void imx6sl_enable_pll_arm(bool enable)
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+{
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+ static u32 saved_pll_arm;
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+ u32 val;
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+
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+ if (enable) {
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+ saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
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+ val |= BM_PLL_ARM_ENABLE;
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+ val &= ~BM_PLL_ARM_POWERDOWN;
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+ writel_relaxed(val, anatop_base + PLL_ARM);
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+ while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
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+ ;
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+ } else {
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+ writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
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+ }
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+}
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+
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void imx6sl_set_wait_clk(bool enter)
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{
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- static unsigned long saved_arm_rate;
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+ static unsigned long saved_arm_div;
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+ int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
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+
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+ /*
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+ * According to hardware design, arm podf change need
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+ * PLL1 clock enabled.
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+ */
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+ if (arm_div_for_wait == ARM_WAIT_DIV_396M)
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+ imx6sl_enable_pll_arm(true);
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if (enter) {
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- unsigned long ipg_rate = clk_get_rate(clks[IMX6SL_CLK_IPG]);
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- unsigned long max_arm_wait_rate = (12 * ipg_rate) / 5;
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- saved_arm_rate = clk_get_rate(clks[IMX6SL_CLK_ARM]);
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- clk_set_rate(clks[IMX6SL_CLK_ARM], max_arm_wait_rate);
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+ saved_arm_div = readl_relaxed(ccm_base + CACRR);
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+ writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
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} else {
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- clk_set_rate(clks[IMX6SL_CLK_ARM], saved_arm_rate);
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+ writel_relaxed(saved_arm_div, ccm_base + CACRR);
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}
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+ while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
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+ ;
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+
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+ if (arm_div_for_wait == ARM_WAIT_DIV_396M)
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+ imx6sl_enable_pll_arm(false);
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}
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static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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@@ -111,6 +180,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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+ anatop_base = base;
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/* type name parent base div_mask */
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clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
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@@ -158,6 +228,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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np = ccm_node;
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base = of_iomap(np, 0);
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WARN_ON(!base);
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+ ccm_base = base;
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/* Reuse imx6q pm code */
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imx6q_pm_set_ccm_base(base);
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Anson Huang