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@@ -103,6 +103,11 @@ static const u32 stoney_mgcg_cgcg_init[] =
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mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
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};
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+static const u32 golden_settings_stoney_common[] =
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+{
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+ mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
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+ mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
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+};
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static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
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{
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@@ -142,6 +147,9 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
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amdgpu_program_register_sequence(adev,
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stoney_mgcg_cgcg_init,
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(const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
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+ amdgpu_program_register_sequence(adev,
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+ golden_settings_stoney_common,
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+ (const u32)ARRAY_SIZE(golden_settings_stoney_common));
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break;
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default:
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break;
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