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@@ -386,21 +386,6 @@ static void push_desc_queue(struct cppi41_channel *c)
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u32 desc_phys;
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u32 reg;
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- desc_phys = lower_32_bits(c->desc_phys);
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- desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
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- WARN_ON(cdd->chan_busy[desc_num]);
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- cdd->chan_busy[desc_num] = c;
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-
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- reg = (sizeof(struct cppi41_desc) - 24) / 4;
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- reg |= desc_phys;
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- cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
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-}
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-
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-static void cppi41_dma_issue_pending(struct dma_chan *chan)
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-{
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- struct cppi41_channel *c = to_cpp41_chan(chan);
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- u32 reg;
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-
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c->residue = 0;
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reg = GCR_CHAN_ENABLE;
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@@ -418,6 +403,21 @@ static void cppi41_dma_issue_pending(struct dma_chan *chan)
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* before starting the dma engine.
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*/
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__iowmb();
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+
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+ desc_phys = lower_32_bits(c->desc_phys);
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+ desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
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+ WARN_ON(cdd->chan_busy[desc_num]);
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+ cdd->chan_busy[desc_num] = c;
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+
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+ reg = (sizeof(struct cppi41_desc) - 24) / 4;
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+ reg |= desc_phys;
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+ cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
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+}
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+
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+static void cppi41_dma_issue_pending(struct dma_chan *chan)
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+{
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+ struct cppi41_channel *c = to_cpp41_chan(chan);
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+
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push_desc_queue(c);
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}
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