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@@ -0,0 +1,675 @@
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+/*
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+ * Copyright (C) 2015 Broadcom Corporation
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/interrupt.h>
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+#include <linux/irqchip/chained_irq.h>
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+#include <linux/irqdomain.h>
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+#include <linux/msi.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_pci.h>
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+#include <linux/pci.h>
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+
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+#include "pcie-iproc.h"
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+
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+#define IPROC_MSI_INTR_EN_SHIFT 11
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+#define IPROC_MSI_INTR_EN BIT(IPROC_MSI_INTR_EN_SHIFT)
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+#define IPROC_MSI_INT_N_EVENT_SHIFT 1
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+#define IPROC_MSI_INT_N_EVENT BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
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+#define IPROC_MSI_EQ_EN_SHIFT 0
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+#define IPROC_MSI_EQ_EN BIT(IPROC_MSI_EQ_EN_SHIFT)
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+
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+#define IPROC_MSI_EQ_MASK 0x3f
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+
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+/* Max number of GIC interrupts */
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+#define NR_HW_IRQS 6
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+
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+/* Number of entries in each event queue */
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+#define EQ_LEN 64
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+
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+/* Size of each event queue memory region */
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+#define EQ_MEM_REGION_SIZE SZ_4K
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+
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+/* Size of each MSI address region */
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+#define MSI_MEM_REGION_SIZE SZ_4K
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+
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+enum iproc_msi_reg {
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+ IPROC_MSI_EQ_PAGE = 0,
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+ IPROC_MSI_EQ_PAGE_UPPER,
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+ IPROC_MSI_PAGE,
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+ IPROC_MSI_PAGE_UPPER,
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+ IPROC_MSI_CTRL,
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+ IPROC_MSI_EQ_HEAD,
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+ IPROC_MSI_EQ_TAIL,
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+ IPROC_MSI_INTS_EN,
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+ IPROC_MSI_REG_SIZE,
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+};
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+
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+struct iproc_msi;
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+
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+/**
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+ * iProc MSI group
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+ *
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+ * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
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+ * event queue.
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+ *
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+ * @msi: pointer to iProc MSI data
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+ * @gic_irq: GIC interrupt
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+ * @eq: Event queue number
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+ */
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+struct iproc_msi_grp {
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+ struct iproc_msi *msi;
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+ int gic_irq;
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+ unsigned int eq;
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+};
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+
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+/**
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+ * iProc event queue based MSI
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+ *
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+ * Only meant to be used on platforms without MSI support integrated into the
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+ * GIC.
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+ *
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+ * @pcie: pointer to iProc PCIe data
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+ * @reg_offsets: MSI register offsets
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+ * @grps: MSI groups
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+ * @nr_irqs: number of total interrupts connected to GIC
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+ * @nr_cpus: number of toal CPUs
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+ * @has_inten_reg: indicates the MSI interrupt enable register needs to be
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+ * set explicitly (required for some legacy platforms)
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+ * @bitmap: MSI vector bitmap
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+ * @bitmap_lock: lock to protect access to the MSI bitmap
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+ * @nr_msi_vecs: total number of MSI vectors
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+ * @inner_domain: inner IRQ domain
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+ * @msi_domain: MSI IRQ domain
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+ * @nr_eq_region: required number of 4K aligned memory region for MSI event
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+ * queues
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+ * @nr_msi_region: required number of 4K aligned address region for MSI posted
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+ * writes
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+ * @eq_cpu: pointer to allocated memory region for MSI event queues
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+ * @eq_dma: DMA address of MSI event queues
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+ * @msi_addr: MSI address
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+ */
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+struct iproc_msi {
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+ struct iproc_pcie *pcie;
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+ const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
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+ struct iproc_msi_grp *grps;
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+ int nr_irqs;
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+ int nr_cpus;
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+ bool has_inten_reg;
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+ unsigned long *bitmap;
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+ struct mutex bitmap_lock;
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+ unsigned int nr_msi_vecs;
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+ struct irq_domain *inner_domain;
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+ struct irq_domain *msi_domain;
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+ unsigned int nr_eq_region;
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+ unsigned int nr_msi_region;
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+ void *eq_cpu;
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+ dma_addr_t eq_dma;
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+ phys_addr_t msi_addr;
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+};
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+
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+static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
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+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
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+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
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+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
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+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
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+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
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+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
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+};
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+
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+static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
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+ { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
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+ { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
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+ { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
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+ { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
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+};
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+
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+static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
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+ enum iproc_msi_reg reg,
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+ unsigned int eq)
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+{
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+ struct iproc_pcie *pcie = msi->pcie;
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+
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+ return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
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+}
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+
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+static inline void iproc_msi_write_reg(struct iproc_msi *msi,
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+ enum iproc_msi_reg reg,
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+ int eq, u32 val)
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+{
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+ struct iproc_pcie *pcie = msi->pcie;
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+
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+ writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
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+}
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+
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+static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
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+{
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+ return (hwirq % msi->nr_irqs);
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+}
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+
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+static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
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+ unsigned long hwirq)
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+{
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+ if (msi->nr_msi_region > 1)
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+ return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
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+ else
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+ return hwirq_to_group(msi, hwirq) * sizeof(u32);
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+}
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+
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+static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
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+{
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+ if (msi->nr_eq_region > 1)
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+ return eq * EQ_MEM_REGION_SIZE;
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+ else
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+ return eq * EQ_LEN * sizeof(u32);
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+}
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+
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+static struct irq_chip iproc_msi_irq_chip = {
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+ .name = "iProc-MSI",
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+};
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+
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+static struct msi_domain_info iproc_msi_domain_info = {
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+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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+ MSI_FLAG_PCI_MSIX,
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+ .chip = &iproc_msi_irq_chip,
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+};
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+
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+/*
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+ * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
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+ * dedicated event queue. Each MSI group can support up to 64 MSI vectors.
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+ *
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+ * The number of MSI groups varies between different iProc SoCs. The total
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+ * number of CPU cores also varies. To support MSI IRQ affinity, we
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+ * distribute GIC interrupts across all available CPUs. MSI vector is moved
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+ * from one GIC interrupt to another to steer to the target CPU.
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+ *
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+ * Assuming:
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+ * - the number of MSI groups is M
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+ * - the number of CPU cores is N
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+ * - M is always a multiple of N
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+ *
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+ * Total number of raw MSI vectors = M * 64
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+ * Total number of supported MSI vectors = (M * 64) / N
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+ */
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+static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
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+{
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+ return (hwirq % msi->nr_cpus);
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+}
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+
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+static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
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+ unsigned long hwirq)
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+{
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+ return (hwirq - hwirq_to_cpu(msi, hwirq));
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+}
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+
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+static int iproc_msi_irq_set_affinity(struct irq_data *data,
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+ const struct cpumask *mask, bool force)
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+{
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+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
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+ int target_cpu = cpumask_first(mask);
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+ int curr_cpu;
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+
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+ curr_cpu = hwirq_to_cpu(msi, data->hwirq);
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+ if (curr_cpu == target_cpu)
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+ return IRQ_SET_MASK_OK_DONE;
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+
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+ /* steer MSI to the target CPU */
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+ data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
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+
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+ return IRQ_SET_MASK_OK;
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+}
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+
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+static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
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+ struct msi_msg *msg)
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+{
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+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
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+ dma_addr_t addr;
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+
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+ addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
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+ msg->address_lo = lower_32_bits(addr);
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+ msg->address_hi = upper_32_bits(addr);
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+ msg->data = data->hwirq;
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+}
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+
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+static struct irq_chip iproc_msi_bottom_irq_chip = {
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+ .name = "MSI",
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+ .irq_set_affinity = iproc_msi_irq_set_affinity,
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+ .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
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+};
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+
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+static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
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+ unsigned int virq, unsigned int nr_irqs,
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+ void *args)
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+{
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+ struct iproc_msi *msi = domain->host_data;
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+ int hwirq;
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+
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+ mutex_lock(&msi->bitmap_lock);
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+
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+ /* Allocate 'nr_cpus' number of MSI vectors each time */
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+ hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
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+ msi->nr_cpus, 0);
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+ if (hwirq < msi->nr_msi_vecs) {
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+ bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
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+ } else {
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+ mutex_unlock(&msi->bitmap_lock);
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+ return -ENOSPC;
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+ }
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+
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+ mutex_unlock(&msi->bitmap_lock);
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+
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+ irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
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+ domain->host_data, handle_simple_irq, NULL, NULL);
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+
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+ return 0;
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+}
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+
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+static void iproc_msi_irq_domain_free(struct irq_domain *domain,
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+ unsigned int virq, unsigned int nr_irqs)
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+{
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+ struct irq_data *data = irq_domain_get_irq_data(domain, virq);
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+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
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+ unsigned int hwirq;
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+
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+ mutex_lock(&msi->bitmap_lock);
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+
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+ hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
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+ bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
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+
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+ mutex_unlock(&msi->bitmap_lock);
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+
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+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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+}
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+
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+static const struct irq_domain_ops msi_domain_ops = {
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+ .alloc = iproc_msi_irq_domain_alloc,
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+ .free = iproc_msi_irq_domain_free,
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+};
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+
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+static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
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+{
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+ u32 *msg, hwirq;
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+ unsigned int offs;
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+
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+ offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
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+ msg = (u32 *)(msi->eq_cpu + offs);
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+ hwirq = *msg & IPROC_MSI_EQ_MASK;
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+
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+ /*
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+ * Since we have multiple hwirq mapped to a single MSI vector,
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+ * now we need to derive the hwirq at CPU0. It can then be used to
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+ * mapped back to virq.
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+ */
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+ return hwirq_to_canonical_hwirq(msi, hwirq);
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+}
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+
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+static void iproc_msi_handler(struct irq_desc *desc)
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+{
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ struct iproc_msi_grp *grp;
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+ struct iproc_msi *msi;
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+ struct iproc_pcie *pcie;
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+ u32 eq, head, tail, nr_events;
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+ unsigned long hwirq;
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+ int virq;
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+
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+ chained_irq_enter(chip, desc);
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+
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+ grp = irq_desc_get_handler_data(desc);
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+ msi = grp->msi;
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+ pcie = msi->pcie;
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+ eq = grp->eq;
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+
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+ /*
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+ * iProc MSI event queue is tracked by head and tail pointers. Head
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+ * pointer indicates the next entry (MSI data) to be consumed by SW in
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+ * the queue and needs to be updated by SW. iProc MSI core uses the
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+ * tail pointer as the next data insertion point.
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+ *
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+ * Entries between head and tail pointers contain valid MSI data. MSI
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+ * data is guaranteed to be in the event queue memory before the tail
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+ * pointer is updated by the iProc MSI core.
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+ */
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+ head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
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+ eq) & IPROC_MSI_EQ_MASK;
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+ do {
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+ tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
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+ eq) & IPROC_MSI_EQ_MASK;
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+
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+ /*
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+ * Figure out total number of events (MSI data) to be
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+ * processed.
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+ */
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+ nr_events = (tail < head) ?
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+ (EQ_LEN - (head - tail)) : (tail - head);
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+ if (!nr_events)
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+ break;
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+
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+ /* process all outstanding events */
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+ while (nr_events--) {
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+ hwirq = decode_msi_hwirq(msi, eq, head);
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+ virq = irq_find_mapping(msi->inner_domain, hwirq);
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+ generic_handle_irq(virq);
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+
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+ head++;
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+ head %= EQ_LEN;
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+ }
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+
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+ /*
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+ * Now all outstanding events have been processed. Update the
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+ * head pointer.
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+ */
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+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
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+
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+ /*
|
|
|
+ * Now go read the tail pointer again to see if there are new
|
|
|
+ * oustanding events that came in during the above window.
|
|
|
+ */
|
|
|
+ } while (true);
|
|
|
+
|
|
|
+ chained_irq_exit(chip, desc);
|
|
|
+}
|
|
|
+
|
|
|
+static void iproc_msi_enable(struct iproc_msi *msi)
|
|
|
+{
|
|
|
+ int i, eq;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ /* Program memory region for each event queue */
|
|
|
+ for (i = 0; i < msi->nr_eq_region; i++) {
|
|
|
+ dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
|
|
|
+
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
|
|
|
+ lower_32_bits(addr));
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
|
|
|
+ upper_32_bits(addr));
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Program address region for MSI posted writes */
|
|
|
+ for (i = 0; i < msi->nr_msi_region; i++) {
|
|
|
+ phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
|
|
|
+
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
|
|
|
+ lower_32_bits(addr));
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
|
|
|
+ upper_32_bits(addr));
|
|
|
+ }
|
|
|
+
|
|
|
+ for (eq = 0; eq < msi->nr_irqs; eq++) {
|
|
|
+ /* Enable MSI event queue */
|
|
|
+ val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
|
|
|
+ IPROC_MSI_EQ_EN;
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Some legacy platforms require the MSI interrupt enable
|
|
|
+ * register to be set explicitly.
|
|
|
+ */
|
|
|
+ if (msi->has_inten_reg) {
|
|
|
+ val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
|
|
|
+ val |= BIT(eq);
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void iproc_msi_disable(struct iproc_msi *msi)
|
|
|
+{
|
|
|
+ u32 eq, val;
|
|
|
+
|
|
|
+ for (eq = 0; eq < msi->nr_irqs; eq++) {
|
|
|
+ if (msi->has_inten_reg) {
|
|
|
+ val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
|
|
|
+ val &= ~BIT(eq);
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
|
|
|
+ }
|
|
|
+
|
|
|
+ val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
|
|
|
+ val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
|
|
|
+ IPROC_MSI_EQ_EN);
|
|
|
+ iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static int iproc_msi_alloc_domains(struct device_node *node,
|
|
|
+ struct iproc_msi *msi)
|
|
|
+{
|
|
|
+ msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
|
|
|
+ &msi_domain_ops, msi);
|
|
|
+ if (!msi->inner_domain)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
|
|
|
+ &iproc_msi_domain_info,
|
|
|
+ msi->inner_domain);
|
|
|
+ if (!msi->msi_domain) {
|
|
|
+ irq_domain_remove(msi->inner_domain);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void iproc_msi_free_domains(struct iproc_msi *msi)
|
|
|
+{
|
|
|
+ if (msi->msi_domain)
|
|
|
+ irq_domain_remove(msi->msi_domain);
|
|
|
+
|
|
|
+ if (msi->inner_domain)
|
|
|
+ irq_domain_remove(msi->inner_domain);
|
|
|
+}
|
|
|
+
|
|
|
+static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
|
|
|
+ irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
|
|
|
+ NULL, NULL);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
|
|
|
+{
|
|
|
+ int i, ret;
|
|
|
+ cpumask_var_t mask;
|
|
|
+ struct iproc_pcie *pcie = msi->pcie;
|
|
|
+
|
|
|
+ for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
|
|
|
+ irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
|
|
|
+ iproc_msi_handler,
|
|
|
+ &msi->grps[i]);
|
|
|
+ /* Dedicate GIC interrupt to each CPU core */
|
|
|
+ if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
|
|
|
+ cpumask_clear(mask);
|
|
|
+ cpumask_set_cpu(cpu, mask);
|
|
|
+ ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
|
|
|
+ if (ret)
|
|
|
+ dev_err(pcie->dev,
|
|
|
+ "failed to set affinity for IRQ%d\n",
|
|
|
+ msi->grps[i].gic_irq);
|
|
|
+ free_cpumask_var(mask);
|
|
|
+ } else {
|
|
|
+ dev_err(pcie->dev, "failed to alloc CPU mask\n");
|
|
|
+ ret = -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ret) {
|
|
|
+ /* Free all configured/unconfigured IRQs */
|
|
|
+ iproc_msi_irq_free(msi, cpu);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
|
|
|
+{
|
|
|
+ struct iproc_msi *msi;
|
|
|
+ int i, ret;
|
|
|
+ unsigned int cpu;
|
|
|
+
|
|
|
+ if (!of_device_is_compatible(node, "brcm,iproc-msi"))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ if (!of_find_property(node, "msi-controller", NULL))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ if (pcie->msi)
|
|
|
+ return -EBUSY;
|
|
|
+
|
|
|
+ msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
|
|
|
+ if (!msi)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ msi->pcie = pcie;
|
|
|
+ pcie->msi = msi;
|
|
|
+ msi->msi_addr = pcie->base_addr;
|
|
|
+ mutex_init(&msi->bitmap_lock);
|
|
|
+ msi->nr_cpus = num_possible_cpus();
|
|
|
+
|
|
|
+ msi->nr_irqs = of_irq_count(node);
|
|
|
+ if (!msi->nr_irqs) {
|
|
|
+ dev_err(pcie->dev, "found no MSI GIC interrupt\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (msi->nr_irqs > NR_HW_IRQS) {
|
|
|
+ dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
|
|
|
+ msi->nr_irqs);
|
|
|
+ msi->nr_irqs = NR_HW_IRQS;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (msi->nr_irqs < msi->nr_cpus) {
|
|
|
+ dev_err(pcie->dev,
|
|
|
+ "not enough GIC interrupts for MSI affinity\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (msi->nr_irqs % msi->nr_cpus != 0) {
|
|
|
+ msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
|
|
|
+ dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
|
|
|
+ msi->nr_irqs);
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (pcie->type) {
|
|
|
+ case IPROC_PCIE_PAXB:
|
|
|
+ msi->reg_offsets = iproc_msi_reg_paxb;
|
|
|
+ msi->nr_eq_region = 1;
|
|
|
+ msi->nr_msi_region = 1;
|
|
|
+ break;
|
|
|
+ case IPROC_PCIE_PAXC:
|
|
|
+ msi->reg_offsets = iproc_msi_reg_paxc;
|
|
|
+ msi->nr_eq_region = msi->nr_irqs;
|
|
|
+ msi->nr_msi_region = msi->nr_irqs;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
|
|
|
+ msi->has_inten_reg = true;
|
|
|
+
|
|
|
+ msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
|
|
|
+ msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
|
|
|
+ sizeof(*msi->bitmap), GFP_KERNEL);
|
|
|
+ if (!msi->bitmap)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!msi->grps)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ for (i = 0; i < msi->nr_irqs; i++) {
|
|
|
+ unsigned int irq = irq_of_parse_and_map(node, i);
|
|
|
+
|
|
|
+ if (!irq) {
|
|
|
+ dev_err(pcie->dev, "unable to parse/map interrupt\n");
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto free_irqs;
|
|
|
+ }
|
|
|
+ msi->grps[i].gic_irq = irq;
|
|
|
+ msi->grps[i].msi = msi;
|
|
|
+ msi->grps[i].eq = i;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Reserve memory for event queue and make sure memories are zeroed */
|
|
|
+ msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
|
|
|
+ msi->nr_eq_region * EQ_MEM_REGION_SIZE,
|
|
|
+ &msi->eq_dma, GFP_KERNEL);
|
|
|
+ if (!msi->eq_cpu) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto free_irqs;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = iproc_msi_alloc_domains(node, msi);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(pcie->dev, "failed to create MSI domains\n");
|
|
|
+ goto free_eq_dma;
|
|
|
+ }
|
|
|
+
|
|
|
+ for_each_online_cpu(cpu) {
|
|
|
+ ret = iproc_msi_irq_setup(msi, cpu);
|
|
|
+ if (ret)
|
|
|
+ goto free_msi_irq;
|
|
|
+ }
|
|
|
+
|
|
|
+ iproc_msi_enable(msi);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+free_msi_irq:
|
|
|
+ for_each_online_cpu(cpu)
|
|
|
+ iproc_msi_irq_free(msi, cpu);
|
|
|
+ iproc_msi_free_domains(msi);
|
|
|
+
|
|
|
+free_eq_dma:
|
|
|
+ dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
|
|
|
+ msi->eq_cpu, msi->eq_dma);
|
|
|
+
|
|
|
+free_irqs:
|
|
|
+ for (i = 0; i < msi->nr_irqs; i++) {
|
|
|
+ if (msi->grps[i].gic_irq)
|
|
|
+ irq_dispose_mapping(msi->grps[i].gic_irq);
|
|
|
+ }
|
|
|
+ pcie->msi = NULL;
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iproc_msi_init);
|
|
|
+
|
|
|
+void iproc_msi_exit(struct iproc_pcie *pcie)
|
|
|
+{
|
|
|
+ struct iproc_msi *msi = pcie->msi;
|
|
|
+ unsigned int i, cpu;
|
|
|
+
|
|
|
+ if (!msi)
|
|
|
+ return;
|
|
|
+
|
|
|
+ iproc_msi_disable(msi);
|
|
|
+
|
|
|
+ for_each_online_cpu(cpu)
|
|
|
+ iproc_msi_irq_free(msi, cpu);
|
|
|
+
|
|
|
+ iproc_msi_free_domains(msi);
|
|
|
+
|
|
|
+ dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
|
|
|
+ msi->eq_cpu, msi->eq_dma);
|
|
|
+
|
|
|
+ for (i = 0; i < msi->nr_irqs; i++) {
|
|
|
+ if (msi->grps[i].gic_irq)
|
|
|
+ irq_dispose_mapping(msi->grps[i].gic_irq);
|
|
|
+ }
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iproc_msi_exit);
|
Bjorn Helgaas
10 роки тому