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@@ -642,6 +642,116 @@ static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
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return 0;
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}
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+/*
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+ * GPWRDN interrupt handler.
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+ *
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+ * The GPWRDN interrupts are those that occur in both Host and
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+ * Device mode while core is in hibernated state.
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+ */
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+static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
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+{
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+ u32 gpwrdn;
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+ int linestate;
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+
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+ gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
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+ /* clear all interrupt */
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+ dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
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+ linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
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+ dev_dbg(hsotg->dev,
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+ "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
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+ gpwrdn);
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+
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+ if ((gpwrdn & GPWRDN_DISCONN_DET) &&
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+ (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
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+ u32 gpwrdn_tmp;
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+
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+ dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
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+
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+ /* Switch-on voltage to the core */
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+ gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
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+ gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
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+ dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
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+ udelay(10);
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+
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+ /* Reset core */
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+ gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
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+ gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
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+ dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
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+ udelay(10);
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+
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+ /* Disable Power Down Clamp */
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+ gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
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+ gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
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+ dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
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+ udelay(10);
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+
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+ /* Deassert reset core */
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+ gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
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+ gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
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+ dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
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+ udelay(10);
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+
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+ /* Disable PMU interrupt */
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+ gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
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+ gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
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+ dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
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+
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+ /* De-assert Wakeup Logic */
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+ gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN);
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+ gpwrdn_tmp &= ~GPWRDN_PMUACTV;
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+ dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN);
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+
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+ hsotg->hibernated = 0;
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+
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+ if (gpwrdn & GPWRDN_IDSTS) {
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+ hsotg->op_state = OTG_STATE_B_PERIPHERAL;
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+ dwc2_core_init(hsotg, false);
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+ dwc2_enable_global_interrupts(hsotg);
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+ dwc2_hsotg_core_init_disconnected(hsotg, false);
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+ dwc2_hsotg_core_connect(hsotg);
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+ } else {
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+ hsotg->op_state = OTG_STATE_A_HOST;
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+
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+ /* Initialize the Core for Host mode */
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+ dwc2_core_init(hsotg, false);
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+ dwc2_enable_global_interrupts(hsotg);
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+ dwc2_hcd_start(hsotg);
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+ }
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+ }
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+
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+ if ((gpwrdn & GPWRDN_LNSTSCHG) &&
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+ (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
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+ dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
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+ if (hsotg->hw_params.hibernation &&
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+ hsotg->hibernated) {
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+ if (gpwrdn & GPWRDN_IDSTS) {
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+ dwc2_exit_hibernation(hsotg, 0, 0, 0);
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+ call_gadget(hsotg, resume);
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+ } else {
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+ dwc2_exit_hibernation(hsotg, 1, 0, 1);
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+ }
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+ }
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+ }
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+ if ((gpwrdn & GPWRDN_RST_DET) && (gpwrdn & GPWRDN_RST_DET_MSK)) {
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+ dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
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+ if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
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+ dwc2_exit_hibernation(hsotg, 0, 1, 0);
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+ }
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+ if ((gpwrdn & GPWRDN_STS_CHGINT) &&
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+ (gpwrdn & GPWRDN_STS_CHGINT_MSK) && linestate) {
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+ dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
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+ if (hsotg->hw_params.hibernation &&
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+ hsotg->hibernated) {
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+ if (gpwrdn & GPWRDN_IDSTS) {
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+ dwc2_exit_hibernation(hsotg, 0, 0, 0);
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+ call_gadget(hsotg, resume);
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+ } else {
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+ dwc2_exit_hibernation(hsotg, 1, 0, 1);
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+ }
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+ }
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+ }
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+}
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+
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/*
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* Common interrupt handler
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*
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@@ -672,6 +782,13 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
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if (gintsts & ~GINTSTS_PRTINT)
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retval = IRQ_HANDLED;
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+ /* In case of hibernated state gintsts must not work */
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+ if (hsotg->hibernated) {
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+ dwc2_handle_gpwrdn_intr(hsotg);
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+ retval = IRQ_HANDLED;
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+ goto out;
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+ }
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+
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if (gintsts & GINTSTS_MODEMIS)
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dwc2_handle_mode_mismatch_intr(hsotg);
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if (gintsts & GINTSTS_OTGINT)
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