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@@ -43,17 +43,11 @@
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static bool pnv_eeh_nb_init = false;
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static int eeh_event_irq = -EINVAL;
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-/**
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- * pnv_eeh_init - EEH platform dependent initialization
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- *
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- * EEH platform dependent initialization on powernv
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- */
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static int pnv_eeh_init(void)
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{
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struct pci_controller *hose;
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struct pnv_phb *phb;
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- /* We require OPALv3 */
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if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
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pr_warn("%s: OPALv3 is required !\n",
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__func__);
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@@ -77,9 +71,9 @@ static int pnv_eeh_init(void)
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/*
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* PE#0 should be regarded as valid by EEH core
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* if it's not the reserved one. Currently, we
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- * have the reserved PE#0 and PE#127 for PHB3
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+ * have the reserved PE#255 and PE#127 for PHB3
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* and P7IOC separately. So we should regard
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- * PE#0 as valid for P7IOC.
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+ * PE#0 as valid for PHB3 and P7IOC.
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*/
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if (phb->ioda.reserved_pe != 0)
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eeh_add_flag(EEH_VALID_PE_ZERO);
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@@ -284,7 +278,6 @@ static int pnv_eeh_post_init(void)
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#endif /* CONFIG_DEBUG_FS */
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}
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-
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return ret;
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}
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@@ -490,7 +483,6 @@ static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
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int opt, ret = 0;
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s64 rc;
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- /* Sanity check on option */
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switch (option) {
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case EEH_OPT_DISABLE:
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return -EPERM;
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@@ -1065,7 +1057,6 @@ static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
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struct pnv_phb *phb = hose->private_data;
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s64 rc;
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- /* Sanity check on error type */
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if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
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type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
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pr_warn("%s: Invalid error type %d\n",
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