arm64: dts: ti: k3-j721e-proc-board-tps65917: Update wiz lane<n>-mode props

Update lane<n>-mode properties in wiz nodes according to the lane use
on tps65917 processor board.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>

arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts

@@ -467,6 +467,13 @@
 	};
 };
 
+&serdes_wiz4 {
+	lane0-mode = <PHY_TYPE_DP>;
+	lane1-mode = <PHY_TYPE_DP>;
+	lane2-mode = <PHY_TYPE_DP>;
+	lane3-mode = <PHY_TYPE_DP>;
+};
+
 &main_i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_i2c0_pins_default>;
@@ -681,6 +688,8 @@
 &serdes_wiz3 {
 	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
 	typec-dir-debounce = <300>;	/* TUSB321, tCCB_DEFAULT 133 ms */
+	lane0-mode = <PHY_TYPE_USB3>;
+	lane1-mode = <PHY_TYPE_USB3>;
 };
 
 &serdes3 {
@@ -738,6 +747,11 @@
 	status = "disabled";
 };
 
+&serdes_wiz0 {
+	lane0-mode = <PHY_TYPE_PCIE>;
+	lane1-mode = <PHY_TYPE_PCIE>;
+};
+
 &serdes0 {
 	serdes0_pcie_link: link@0 {
 		reg = <0>;
@@ -748,6 +762,11 @@
 	};
 };
 
+&serdes_wiz1 {
+	lane0-mode = <PHY_TYPE_PCIE>;
+	lane1-mode = <PHY_TYPE_PCIE>;
+};
+
 &serdes1 {
 	serdes1_pcie_link: link@0 {
 		reg = <0>;
@@ -758,6 +777,11 @@
 	};
 };
 
+&serdes_wiz2 {
+	lane0-mode = <PHY_TYPE_PCIE>;
+	lane1-mode = <PHY_TYPE_PCIE>;
+};
+
 &serdes2 {
 	serdes2_pcie_link: link@0 {
 		reg = <0>;