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@@ -1182,6 +1182,40 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = {
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},
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};
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+/*
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+ * 'gpu' class
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+ * 3d graphics accelerator
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+ */
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+
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+static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
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+ .rev_offs = 0xfe00,
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+ .sysc_offs = 0xfe10,
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+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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+ .sysc_fields = &omap_hwmod_sysc_type2,
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+};
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+
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+static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
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+ .name = "gpu",
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+ .sysc = &dra7xx_gpu_sysc,
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+};
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+
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+static struct omap_hwmod dra7xx_gpu_hwmod = {
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+ .name = "gpu",
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+ .class = &dra7xx_gpu_hwmod_class,
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+ .clkdm_name = "gpu_clkdm",
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+ .main_clk = "gpu_core_gclk_mux",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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/*
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* 'hdq1w' class
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*
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@@ -3339,6 +3373,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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+/* l3_main_1 -> gpu */
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+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
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+ .master = &dra7xx_l3_main_1_hwmod,
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+ .slave = &dra7xx_gpu_hwmod,
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+ .clk = "l3_iclk_div",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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/* l4_per1 -> hdq1w */
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static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
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.master = &dra7xx_l4_per1_hwmod,
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@@ -4077,6 +4119,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
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&dra7xx_l4_per1__gpio7,
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&dra7xx_l4_per1__gpio8,
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&dra7xx_l3_main_1__gpmc,
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+ &dra7xx_l3_main_1__gpu,
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&dra7xx_l4_per1__hdq1w,
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&dra7xx_l4_per1__i2c1,
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&dra7xx_l4_per1__i2c2,
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